Invention Grant
- Patent Title: Design of low inductance embedded capacitor layer connections
- Patent Title (中): 低电感嵌入式电容层连接设计
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Application No.: US11516377Application Date: 2006-09-06
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Publication No.: US07456459B2Publication Date: 2008-11-25
- Inventor: Lixi Wan
- Applicant: Lixi Wan
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119 ; H01L29/04 ; H01L29/12 ; H01L31/036 ; H01L31/112 ; H01L29/786 ; H01L29/80 ; H01L29/00

Abstract:
The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.
Public/Granted literature
- US20070108552A1 Design of low inductance embedded capacitor layer connections Public/Granted day:2007-05-17
Information query
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