发明授权
- 专利标题: Multi-thread parallel segment scan simulation of chip element performance
- 专利标题(中): 多线程并行段扫描模拟芯片元件性能
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申请号: US11040140申请日: 2005-01-21
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公开(公告)号: US07509552B2公开(公告)日: 2009-03-24
- 发明人: Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
- 申请人: Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
- 申请人地址: US NY Armonk
- 专利权人: International Business Machiens Corporation
- 当前专利权人: International Business Machiens Corporation
- 当前专利权人地址: US NY Armonk
- 代理商 Lynn L. Augspurger; Graham S. Jones
- 主分类号: G01R31/28
- IPC分类号: G01R31/28 ; G06F7/02
摘要:
A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
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