Multi-thread parallel segment scan simulation of chip element performance
    1.
    发明授权
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US07509552B2

    公开(公告)日:2009-03-24

    申请号:US11040140

    申请日:2005-01-21

    IPC分类号: G01R31/28 G06F7/02

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,可以在初始时间停止模拟测试仪的正常功能,启动扫描时钟,并记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance
    2.
    发明申请
    Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance 失效
    多线并行段扫描模拟芯片元件性能

    公开(公告)号:US20070255997A1

    公开(公告)日:2007-11-01

    申请号:US11754941

    申请日:2007-05-29

    IPC分类号: H03M13/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品。 该方法,系统和程序产品停止模拟测试用例的正常功能,启动扫描时钟,在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-thread parallel segment scan simulation of chip element performance
    3.
    发明申请
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US20060168497A1

    公开(公告)日:2006-07-27

    申请号:US11040140

    申请日:2005-01-21

    IPC分类号: H03M13/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品。 该方法,系统和程序产品停止模拟测试用例的正常功能,启动扫描时钟,在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-thread parallel segment scan simulation of chip element performance
    4.
    发明授权
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US07559002B2

    公开(公告)日:2009-07-07

    申请号:US11754941

    申请日:2007-05-29

    IPC分类号: G01R31/28 G06F11/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品可以停止模拟测试用例的正常功能,启动扫描时钟,并将扫描环数据的第一个“快照”记录在 最初的时间。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。