Multi-thread parallel segment scan simulation of chip element performance
    1.
    发明授权
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US07509552B2

    公开(公告)日:2009-03-24

    申请号:US11040140

    申请日:2005-01-21

    IPC分类号: G01R31/28 G06F7/02

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,可以在初始时间停止模拟测试仪的正常功能,启动扫描时钟,并记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance
    2.
    发明申请
    Multi-Thread Parallel Segment Scan Simulation of Chip Element Performance 失效
    多线并行段扫描模拟芯片元件性能

    公开(公告)号:US20070255997A1

    公开(公告)日:2007-11-01

    申请号:US11754941

    申请日:2007-05-29

    IPC分类号: H03M13/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品。 该方法,系统和程序产品停止模拟测试用例的正常功能,启动扫描时钟,在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-thread parallel segment scan simulation of chip element performance
    3.
    发明申请
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US20060168497A1

    公开(公告)日:2006-07-27

    申请号:US11040140

    申请日:2005-01-21

    IPC分类号: H03M13/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product built upon the underlying hardware design of the microprocessor. The method, system, and program product stops normal functions of a simulation testcase, starts the scan clocks, records a first “snap shot” of the scan ring data at this initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品。 该方法,系统和程序产品停止模拟测试用例的正常功能,启动扫描时钟,在初始时刻记录扫描环数据的第一个“快照”。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Multi-thread parallel segment scan simulation of chip element performance
    4.
    发明授权
    Multi-thread parallel segment scan simulation of chip element performance 失效
    多线程并行段扫描模拟芯片元件性能

    公开(公告)号:US07559002B2

    公开(公告)日:2009-07-07

    申请号:US11754941

    申请日:2007-05-29

    IPC分类号: G01R31/28 G06F11/00

    CPC分类号: G06F17/5022

    摘要: A microprocessor simulation method, system, and program product, which are built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.

    摘要翻译: 基于微处理器底层硬件设计的微处理器仿真方法,系统和程序产品可以停止模拟测试用例的正常功能,启动扫描时钟,并将扫描环数据的第一个“快照”记录在 最初的时间。 然后硬件逻辑使用当前的扫描数据旋转(移动)扫描环,并且当扫描时钟停止时(扫描时钟的停止基于扫描环上的锁存器的数量被控制),另一个“快照” 的扫描环数据。 比较“快照”,如果“快照”都相同,则功能扫描成功。 但是,如果功能扫描验证无法正确旋转扫描链,也就是说,如果两个“快照”中的一些闩锁不匹配,则有必要将断点定位在大量扫描锁存器内。

    Method, system and computer program product for register management in a simulation environment
    5.
    发明申请
    Method, system and computer program product for register management in a simulation environment 失效
    方法,系统和计算机程序产品,用于模拟环境中的注册管理

    公开(公告)号:US20050251379A1

    公开(公告)日:2005-11-10

    申请号:US10835324

    申请日:2004-04-29

    CPC分类号: G06F17/5022

    摘要: A method for register management in a simulation environment including receiving an instruction from an instruction unit decode pipeline. An address generation interlock (AGI) function is executed in the simulation environment if the instruction is an AGI instruction. The executing an AGI function is responsive to a pool of registers controlled by a register manager and to the instruction. An early AGI function is executed in the simulation environment if the instruction is an early AGI instruction. The executing an early AGI function is responsive to the pool of registers and to the instruction.

    摘要翻译: 一种在模拟环境中的寄存器管理方法,包括从指令单元解码流水线接收指令。 如果指令是AGI指令,则在仿真环境中执行地址生成互锁(AGI)功能。 执行AGI功能响应于由寄存器管理器和指令控制的寄存器池。 如果指令是早期AGI指令,则在仿真环境中执行早期AGI功能。 执行早期AGI功能可以响应寄存器池和指令。

    Conveyor belts with thin film sensor-activating coating
    6.
    发明申请
    Conveyor belts with thin film sensor-activating coating 失效
    输送带带薄膜传感器激活涂层

    公开(公告)号:US20060180440A1

    公开(公告)日:2006-08-17

    申请号:US11057004

    申请日:2005-02-11

    IPC分类号: B65G43/00

    CPC分类号: G09F19/22

    摘要: A conveyor belt device wherein a detectable coating, such as in the form of a thin film, overlies selected portions of a conveyor belt substrate surface. Suitable detectable coatings include materials that are inductive, conductive, magnetic, reflective, fluorescent and color-indicating or a combination thereof. Also disclosed are associated or corresponding conveyor belt assemblies and methods of making.

    摘要翻译: 一种输送带装置,其中诸如薄膜形式的可检测涂层覆盖在输送带基材表面的选定部分上。 合适的可检测涂层包括感应,导电,磁性,反射,荧光和颜色指示的材料或其组合。 还公开了相关联或相应的传送带组件和制造方法。

    Coupler guard system
    7.
    发明授权

    公开(公告)号:US10995477B2

    公开(公告)日:2021-05-04

    申请号:US15910003

    申请日:2018-03-01

    申请人: William Lewis

    发明人: William Lewis

    摘要: A coupler guard configured to protect an aux coupler assembly from side impacts in the rough use environment of a loader. The coupler guard comprises an encasement and a side plate. The loader comprises the aux coupler assembly and a hinge extension. The encasement wraps around a top portion and interior side of the aux coupler assembly. The side plate attaches to a portion of the encasement and protect an exterior side portion of the aux coupler assembly. A screw assemblies selectively attaches the encasement to the side plate. A ring attaches to a portion of the side plate. The ring selectively wraps around a portion of the hinge extension of the loader. A ring screw assembly selectively holds the ring and the rest of the coupler guard to the hinge extension. An edge trim selectively sits on top of a portion of a first arm.

    System and method for electronic record keeping
    10.
    发明申请
    System and method for electronic record keeping 审中-公开
    电子记录系统和方法

    公开(公告)号:US20070124278A1

    公开(公告)日:2007-05-31

    申请号:US11589064

    申请日:2006-10-30

    IPC分类号: G06F17/30

    CPC分类号: G16B50/00

    摘要: A system and method of keeping records includes recording information and metadata associated with the information. The metadata is protected from changes. The information can be displayed to a second user for acknowledgement. Acknowledgement by the second user can also be recorded. The metadata can provide an audit trail for reviewing additions, deletions and changes to the records.

    摘要翻译: 保存记录的系统和方法包括记录与信息相关联的信息和元数据。 元数据不受更改的保护。 该信息可以显示给第二用户以进行确认。 也可以记录第二用户的确认。 元数据可以提供审核跟踪,用于查看记录的添加,删除和更改。