Invention Grant
- Patent Title: Multi-thread parallel segment scan simulation of chip element performance
- Patent Title (中): 多线程并行段扫描模拟芯片元件性能
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Application No.: US11040140Application Date: 2005-01-21
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Publication No.: US07509552B2Publication Date: 2009-03-24
- Inventor: Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
- Applicant: Wei-Yi Xiao , Dean G. Blair , Thomas Ruane , William Lewis
- Applicant Address: US NY Armonk
- Assignee: International Business Machiens Corporation
- Current Assignee: International Business Machiens Corporation
- Current Assignee Address: US NY Armonk
- Agent Lynn L. Augspurger; Graham S. Jones
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G06F7/02

Abstract:
A microprocessor simulation method, which is built upon the underlying hardware design of the microprocessor, stop normal functions of a simulation testcase, start the scan clocks, and record a first “snap shot” of the scan ring data at an initial time. The hardware logic then rotates (shifts) the scan ring using the current scan data, and when the scan clock stops (where the stop of the scan clock is controlled based on the number of latches on the scan ring), another “snap shot” of scan ring data is taken. The “snap shots” are compared and if both of the “snap shots” are identical the functional scan is successful. But if the functional scan verification fails to rotate the scan chain correctly, that is, if some of the latches do not match in the two “snap shots,” it becomes necessary to locate the broken spot within the large number of scan latches.
Public/Granted literature
- US20060168497A1 Multi-thread parallel segment scan simulation of chip element performance Public/Granted day:2006-07-27
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