发明授权
- 专利标题： Method of fabricating semiconductor integrated circuit device
- 专利标题（中）： 制造半导体集成电路器件的方法
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申请号： US11950152申请日： 2007-12-04
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公开(公告)号： US07553766B2公开(公告)日： 2009-06-30
- 发明人: Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- 申请人： Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Antonelli, Terry, Stout & Kraus, LLP.
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
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