发明授权
- 专利标题： Apparatus and methods for adjusting performance of integrated circuits
- 专利标题（中）： 用于调整集成电路性能的装置和方法
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申请号： US11535065申请日： 2006-09-26
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公开(公告)号： US07573317B2公开(公告)日： 2009-08-11
- 发明人: David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
- 申请人： David Lewis , Vaughn Betz , Irfan Rahim , Peter McElheny , Yow-Juang W. Liu , Bruce Pedersen
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Law Offices of Maximilian R. Peterson
- 主分类号： H03K3/01
- IPC分类号： H03K3/01
摘要：
A programmable logic device (PLD) includes a delay circuit and a body-bias generator. The delay circuit has a delay configured to represent a delay of user circuit implement in the PLD. The body-bias generator is configured to adjust the body bias of a transistor within the user circuit. The body-bias generator adjusts the body bias of the transistor in response to a level derived from the signal propagation delay of the delay circuit.