发明授权
- 专利标题: Three-dimensional package and method of making the same
- 专利标题(中): 三维包装及其制作方法
-
申请号: US11584546申请日: 2006-10-23
-
公开(公告)号: US07642132B2公开(公告)日: 2010-01-05
- 发明人: Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
- 申请人: Min-Lung Huang , Wei-Chung Wang , Po-Jen Cheng , Kuo-Chung Yee , Ching-Huei Su , Jian-Wen Lo , Chian-Chi Lin
- 申请人地址: TW Kaohsiung
- 专利权人: Advanced Semiconductor Engineering, Inc.
- 当前专利权人: Advanced Semiconductor Engineering, Inc.
- 当前专利权人地址: TW Kaohsiung
- 代理机构: Volentine & Whitt, P.L.L.C.
- 优先权: TW95102837A 20060125
- 主分类号: H01L21/44
- IPC分类号: H01L21/44
摘要:
The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.
公开/授权文献
- US20070172982A1 Three-dimensional package and method of making the same 公开/授权日:2007-07-26
信息查询
IPC分类: