公开(公告)号：US20130277829A1

公开(公告)日：2013-10-24

申请号：US13452636

申请日：2012-04-20

Applicant: Kuo-Chung Yee ,  Chun Hui Yu

Inventor： Kuo-Chung Yee ,  Chun Hui Yu

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/10 ,  H01L24/81 ,  H01L24/97 ,  H01L2224/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/81 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a holding chamber in the redistribution layer, attaching an integrated circuit die on the first side of the packaging component, wherein an interconnect bump of the integrated circuit die is inserted into the holding chamber, applying a reflow process to the integrated circuit die and the packaging component and forming an encapsulation layer on the packaging component.

Abstract translation: 一种制造三维集成电路的方法包括在包装部件的第一侧上形成再分配层，在再分布层中形成保持室，将集成电路管芯附接在包装部件的第一侧上，其中互连凸块 的集成电路管芯插入到保持室中，对集成电路管芯和封装部件进行回流处理，并在封装部件上形成封装层。

公开(公告)号：US20130020703A1

公开(公告)日：2013-01-24

申请号：US13560722

申请日：2012-07-27

Applicant: Kuo-Chung Yee ,  Meng-Jen Wang

Inventor： Kuo-Chung Yee ,  Meng-Jen Wang

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/221 ,  H01L2224/2518 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00015 ,  H01L2924/00

Abstract: The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

Abstract translation: 本发明涉及一种制造可堆叠包装的方法。 该方法包括以下步骤：（a）提供第一载体; （b）在所述第一载体上设置至少一个芯片; （c）形成模塑料以封装芯片; （d）移除第一载体; （e）形成第一再分布层和至少一个第一凸起; （f）提供第二载体; （g）设置在第二载体上; （h）去除芯片的一部分和模塑料的一部分; （i）形成第二重分布层; 和（j）移除第二载体。 因此，第二再分配层使得可堆叠封装具有更多的灵活性被利用。

公开(公告)号：US08288853B2

公开(公告)日：2012-10-16

申请号：US12615852

申请日：2009-11-10

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: A package comprises a first unit including a semiconductor body, a hole, an isolation layer, a conductive layer and a solder. The semiconductor body has a first surface having a pad and a protection layer exposing the pad. The hole penetrates the semiconductor body. The isolation layer is disposed on the side wall of the hole. The conductive layer covers the pad, a part of the protection layer, and the isolation layer. The lower end of the conductive layer extends to below a second surface of the semiconductor body. The solder is disposed in the hole, and is electrically connected to the pad via the conductive layer. A second unit similar to the first unit and stacked thereon includes a lower end of a second conductive layer that extends to below a second surface of a second semiconductor body and contacts the upper end of the first solder.

Abstract translation: 封装包括包括半导体本体，孔，隔离层，导电层和焊料的第一单元。 半导体本体具有第一表面，其具有衬垫和暴露衬垫的保护层。 孔穿透半导体本体。 隔离层设置在孔的侧壁上。 导电层覆盖焊盘，保护层的一部分和隔离层。 导电层的下端延伸到半导体本体的第二表面的下方。 焊料设置在孔中，并通过导电层与焊盘电连接。 类似于第一单元并且堆叠在其上的第二单元包括延伸到第二半导体本体的第二表面下方并接触第一焊料的上端的第二导电层的下端。

公开(公告)号：US07642132B2

公开(公告)日：2010-01-05

申请号：US11584546

申请日：2006-10-23

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L21/44

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

Abstract: The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

Abstract translation: 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

公开(公告)号：US07528053B2

公开(公告)日：2009-05-05

申请号：US11645042

申请日：2006-12-26

Applicant: Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

Inventor： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

IPC: H01L21/46 ,  H01L21/4763

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/00012

Abstract: A three-dimensional package and a method of making the same including providing a wafer; forming at least one blind hole in the wafer; forming an isolation layer on the side wall of the blind hole; forming a conductive layer on the isolation layer; forming a dry film on the conductive layer; filling the blind hole with metal; removing the dry film, and patterning the conductive layer; removing a part of the metal in the blind hole to form a space; removing a part of the second surface of the wafer and a part of the isolation layer, to expose a part of the conductive layer; forming a solder on the lower end of the conductive layer, the melting point of the solder is lower than the metal; stacking a plurality of the wafers, and performing a reflow process; and cutting the stacked wafers, to form three-dimensional packages.

Abstract translation: 三维封装及其制造方法，包括提供晶片; 在晶片中形成至少一个盲孔; 在盲孔的侧壁上形成隔离层; 在隔离层上形成导电层; 在导电层上形成干膜; 用金属填充盲孔; 去除干膜，图案化导电层; 去除盲孔中的金属的一部分以形成空间; 去除所述晶片的所述第二表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; 在导电层的下端形成焊料，焊料的熔点低于金属; 堆叠多个晶片，并进行回流处理; 并切割堆叠的晶片，以形成三维封装。

公开(公告)号：US20080185707A1

公开(公告)日：2008-08-07

申请号：US12062203

申请日：2008-04-03

Applicant: Kuo Chung YEE

Inventor： Kuo Chung YEE

IPC: H01L23/48

CPC classification number: H01L27/14683 ,  H01L23/3114 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package structure comprises a chip, a plurality of pad extension traces, a plurality of via holes, a lid and a plurality of metal traces, wherein the chip has an optical component and a plurality of pads disposed on its active surface; pad extension traces are electrically connected to the pads; the via holes penetrate the chip and are electrically connected to the pad extension traces and exposed out of side surfaces of the semiconductor package structure; the lid is adhered onto the active surface of the chip; and the plurality of metal traces is disposed on the back surface of the chip, electrically connected to the plurality of via holes, and used to define a plurality of solder pads thereon. The present invention also provides a method for manufacturing the semiconductor package structure.

Abstract translation: 半导体封装结构包括芯片，多个焊盘扩展迹线，多个通孔，盖子和多个金属迹线，其中芯片具有光学部件和设置在其有效表面上的多个焊盘; 焊盘延伸迹线电连接到焊盘; 通孔穿透芯片并且电连接到焊盘延伸迹线并暴露在半导体封装结构的侧表面之外; 盖子粘附到芯片的有效表面上; 并且多个金属迹线设置在芯片的背面，电连接到多个通孔，并用于在其上限定多个焊盘。 本发明还提供一种半导体封装结构的制造方法。

公开(公告)号：US07247267B2

公开(公告)日：2007-07-24

申请号：US10710906

申请日：2004-08-12

Applicant: Jen-Chieh Kao ,  Kuo-Chung Yee

Inventor： Jen-Chieh Kao ,  Kuo-Chung Yee

IPC: B29C70/72 ,  H01L21/56

CPC classification number: B29C45/0025 ,  B29C45/14639 ,  H01L21/565 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

Abstract translation: 提供了一种用于模制安装在封装衬底上的半导体器件的模具。 模具包括顶模和底模。 顶部模具具有顶部流道，至少第一模拟流道和多个模具腔。 第一个虚拟跑步者与顶级跑步者相连，顶级赛跑者延伸到模具腔之间的空间。 用于容纳半导体器件的模腔连接到顶部流道。 底模具有底流道和至少第二模拟流道。 第二个虚拟跑步者与底下的跑步者相连。 第二虚拟跑步者位于上方，但是通过封装衬底与第一虚拟跑步者分离。

公开(公告)号：US20050042844A1

公开(公告)日：2005-02-24

申请号：US10919178

申请日：2004-08-16

Applicant: Kuo-Chung Yee

Inventor： Kuo-Chung Yee

IPC: H01L21/00 ,  H01L21/78

CPC classification number: B81C1/00333 ,  H01L21/67092 ,  H01L21/78

Abstract: The present invention relates to a method of making a package structure by dicing a wafer from the backside surface thereof comprising: (a) providing a first wafer having a active surface, a backside surface and a plurality of scribe lines defining a plurality of chips, wherein each chip has an annular body thereon; (b) dicing the first wafer from the active surface to form a reference coordinate; (c) providing a second wafer; (d) covering and joining the second wafer to the first wafer to form a plurality of cavities; and (e) dicing the corresponding positions of the scribe lines of the first wafer from the backside surface thereof according to the predetermined distance from the reference coordinate so as to form an individual package structure. As a result, the manufacture time is reduced.

Abstract translation: 本发明涉及通过从其背面切割晶片来制造封装结构的方法，包括：（a）提供具有有源表面的第一晶片，背面和限定多个芯片的多个划线， 其中每个芯片在其上具有环形体; （b）从活性表面切割第一晶片以形成参考坐标; （c）提供第二晶片; （d）将第二晶片覆盖并接合到第一晶片以形成多个空腔; 并且（e）根据与参考坐标的预定距离，从其背面切割第一晶片的划线的对应位置，以形成单独的封装结构。 结果，制造时间缩短。

公开(公告)号：US06822324B2

公开(公告)日：2004-11-23

申请号：US10352042

申请日：2003-01-28

Applicant: Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao ,  Chih-Lung Chen ,  Hsing-Jung Liau

Inventor： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao ,  Chih-Lung Chen ,  Hsing-Jung Liau

IPC: H01L2310

CPC classification number: H01L23/055 ,  H01L23/04 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Abstract translation: 具有空腔的晶片级封装包括芯片，基板和密封构件。 芯片具有微型器件和电连接到微器件的多个接合焊盘。 衬底具有对应并电连接到接合焊盘的多个通孔导电孔。 芯片上的每个接合焊盘设置有用于将焊盘电连接到导电通孔的导电凸块。 密封构件围绕包装以形成密封腔。 本发明还提供一种用于制造具有空腔的晶片级封装的方法。

公开(公告)号：US06768207B2

公开(公告)日：2004-07-27

申请号：US10392851

申请日：2003-03-21

Applicant: Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

Inventor： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

IPC: H01L2348

CPC classification number: H01L25/50 ,  H01L23/10 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multichip wafer-level package includes a first chip, a second chip, a bump ring and a plurality of bumps. The first chip has a semiconductor device, a first bonding ring surrounding the semiconductor device, a plurality of internal bonding pads disposed within the first bonding ring and electrically connected to the semiconductor device, and a plurality of external bonding pads disposed outside the first bonding ring and electrically connected to the semiconductor device for electrically connecting to an external circuit. The second chip has an electronic device, a plurality of bonding pads electrically connected to the electronic device and corresponding to the internal bonding pads of the first chip, and a second bonding ring corresponding to the first bonding ring of the first chip. The bump ring is disposed between the first bonding ring of the first chip and the second bonding ring of the second chip for bonding the first and the second chips so as to form a cavity for accommodating the semiconductor device. The bumps electrically connect the internal bonding pads of the first chip to the bonding pads of the second chip.

Abstract translation: 多芯片晶片级封装包括第一芯片，第二芯片，凸块环和多个凸块。 第一芯片具有半导体器件，围绕半导体器件的第一接合环，设置在第一接合环内并电连接到半导体器件的多个内部接合焊盘，以及设置在第一接合环外侧的多个外部接合焊盘 并且电连接到半导体器件用于电连接到外部电路。 第二芯片具有电子器件，电连接到电子器件并对应于第一芯片的内部接合焊盘的多个接合焊盘以及与第一芯片的第一接合环相对应的第二接合环。 凸块环设置在第一芯片的第一接合环和第二芯片的第二接合环之间，用于接合第一和第二芯片，以形成用于容纳半导体器件的空腔。 凸块将第一芯片的内部焊盘电连接到第二芯片的焊盘。