Invention Grant
US07669083B2 System and method for re-shuffling test case instruction orders for processor design verification and validation
有权
用于处理器设计验证和验证的重新洗牌测试用例指令命令的系统和方法
- Patent Title: System and method for re-shuffling test case instruction orders for processor design verification and validation
- Patent Title (中): 用于处理器设计验证和验证的重新洗牌测试用例指令命令的系统和方法
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Application No.: US11853130Application Date: 2007-09-11
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Publication No.: US07669083B2Publication Date: 2010-02-23
- Inventor: Sampan Arora , Sandip Bag , Vinod Bussa , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Batchu Naga Venkata Satyanarayana , Shiraz Mohammad Zaman
- Applicant: Sampan Arora , Sandip Bag , Vinod Bussa , Shubhodeep Roy Choudhury , Manoj Dusanapudi , Sunil Suresh Hatti , Shakti Kapoor , Batchu Naga Venkata Satyanarayana , Shiraz Mohammad Zaman
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: VanLeeuwen & VanLeeuwen
- Agent Matthew B. Talpis
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor.
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