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    System and method for testing SLB and TLB cells during processor design verification and validation
    3.
    发明授权
    System and method for testing SLB and TLB cells during processor design verification and validation 有权
    在处理器设计验证和验证期间测试SLB和TLB单元的系统和方法

    公开(公告)号：US07797650B2

    公开(公告)日：2010-09-14

    申请号：US11853163

    申请日：2007-09-11

    申请人： Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana

    发明人： Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana

    IPC分类号： G06F17/50 ,  G06F9/44 ,  G06F13/10

    CPC分类号： G06F11/26

    摘要： A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.

    摘要翻译： 提出了一种用于重新执行测试用例并修改测试用例的有效地址，有效段标识符（ESID）和虚拟段标识符（VSID）的系统和方法，以便对处理器的SLB和TLB单元进行全面测试。 测试用例生成器生成测试用例，其包括测试用例有效地址的初始集合，初始的ESID集合和初始的VSID集合。 测试用例执行器使用有效的地址算术函数和虚拟地址算术函数来修改每个重新执行的测试用例有效地址，ESID和VSID，而每个SLB和TLB中的每个位都设置/取消每个位 条目。 在一个实施例中，本文描述的本发明顺序地移动其ESID以单位增量的段后续缓冲区条目，以便完全测试每个SLB条目内的每个ESID比特位置。

    System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation
    4.
    发明申请
    System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation 有权
    在处理器设计验证和验证期间测试SLB和TLB单元的系统和方法

    公开(公告)号：US20090070632A1

    公开(公告)日：2009-03-12

    申请号：US11853163

    申请日：2007-09-11

    申请人： Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana

    发明人： Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Batchu Naga Venkata Satyanarayana

    IPC分类号： G06F11/26

    CPC分类号： G06F11/26

    摘要： A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry.

    摘要翻译： 提出了一种用于重新执行测试用例并修改测试用例的有效地址，有效段标识符（ESID）和虚拟段标识符（VSID）的系统和方法，以便对处理器的SLB和TLB单元进行全面测试。 测试用例生成器生成测试用例，其包括测试用例有效地址的初始集合，初始的ESID集合和初始的VSID集合。 测试用例执行器使用有效的地址算术函数和虚拟地址算术函数来修改每个重新执行的测试用例有效地址，ESID和VSID，而每个SLB和TLB中的每个位都设置/取消每个位 条目。 在一个实施例中，本文描述的本发明顺序地移动其ESID以单位增量的段后续缓冲区条目，以便完全测试每个SLB条目内的每个ESID比特位置。

    System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation
    5.
    发明授权
    System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation 有权
    通过在多个测试模式进行处理器设计验证和验证后计算CRC计算来提高错误检查性能的系统和方法

    公开(公告)号：US07739570B2

    公开(公告)日：2010-06-15

    申请号：US11779385

    申请日：2007-07-18

    申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    IPC分类号： G01R31/28 ,  G06F11/00

    CPC分类号： G06F11/261 ,  G06F11/263

    摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

    摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

    System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation
    6.
    发明申请
    System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation 有权
    通过计算处理器设计验证和验证的多个测试模式后的CRC计算来增加错误检查性能的系统和方法

    公开(公告)号：US20090024873A1

    公开(公告)日：2009-01-22

    申请号：US11779385

    申请日：2007-07-18

    申请人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    发明人： Sandip Bag ,  Shubhodeep Roy Choudhury ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Rahul Sharad Moharil

    IPC分类号： G06F11/263

    CPC分类号： G06F11/261 ,  G06F11/263

    摘要： A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns.

    摘要翻译： 提出了通过在多个测试模式之间共享存储器并且在每次测试模式执行一次之后执行结果检查来减少验证时间的系统和方法。 测试模式生成器生成多个测试模式集，每个测试模式集包含多个测试模式。 每个测试模式集由相应的线程/处理器执行，直到测试模式集中包含的每个测试模式至少执行一次。 在所有测试模式至少执行一次之后，测试模式执行器执行内存错误检测检查，以确定系统是否正常运行。 由于本文描述的发明等待直到所有测试模式在执行存储器错误检测检查之前已经执行，所以花费更少的时间用于存储器错误检测检查，这允许更多的时间来执行测试模式。

    System and method for pseudo-random test pattern memory allocation for processor design verification and validation
    7.
    发明授权
    System and method for pseudo-random test pattern memory allocation for processor design verification and validation 失效
    用于处理器设计验证和验证的伪随机测试模式存储器分配的系统和方法

    公开(公告)号：US07584394B2

    公开(公告)日：2009-09-01

    申请号：US11779394

    申请日：2007-07-18

    申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/00

    CPC分类号： G06F11/263

    摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

    摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果进行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。

    System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation
    8.
    发明申请
    System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation 失效
    用于处理器设计验证和验证的伪随机测试模式存储器分配的系统和方法

    公开(公告)号：US20090024891A1

    公开(公告)日：2009-01-22

    申请号：US11779394

    申请日：2007-07-18

    申请人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    发明人： Shubhodeep Roy Choudhury ,  Sandip Bag ,  Manoj Dusanapudi ,  Sunil Suresh Hatti ,  Shakti Kapoor ,  Bhavani Shringari Nanjundiah

    IPC分类号： G06F11/30

    CPC分类号： G06F11/263

    摘要： A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units.

    摘要翻译： 提出了一种用于伪随机分配页表存储器以用于测试图案指令以在处理器执行期间产生复杂测试场景的系统和方法。 本文描述的发明在跨处理器和多个测试模式之间分配页表存储器，例如当处理器执行“n”个测试模式时。 另外，使用“真”共享模式或“假”共享模式来分配页表存储器。 虚假共享模式提供了对测试模式结果执行错误检测检查的灵活性。 此外，由于处理器包括诸如高速缓存，TLB（翻译旁边缓冲器），SLB（分片旁边缓冲器），MMU（存储器管理单元）和数据/指令预取引擎的子单元， 测试模式有效地使用页表存储器来测试每个子单元。