Invention Grant
US07816271B2 Methods for forming contacts for dual stress liner CMOS semiconductor devices
有权
双应力衬垫CMOS半导体器件接触形成方法
- Patent Title: Methods for forming contacts for dual stress liner CMOS semiconductor devices
- Patent Title (中): 双应力衬垫CMOS半导体器件接触形成方法
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Application No.: US11778039Application Date: 2007-07-14
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Publication No.: US07816271B2Publication Date: 2010-10-19
- Inventor: Kyoung Woo Lee , Ja Hum Ku , WanJae Park , Chong Kwang Chang , Theodorus E. Standaert
- Applicant: Kyoung Woo Lee , Ja Hum Ku , WanJae Park , Chong Kwang Chang , Theodorus E. Standaert
- Applicant Address: KR Suwon-Si US NY Armonk
- Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
- Current Assignee: Samsung Electronics Co., Ltd.,International Business Machines Corporation
- Current Assignee Address: KR Suwon-Si US NY Armonk
- Agency: F. Chau & Associates, LLC
- Main IPC: H01L21/311
- IPC: H01L21/311

Abstract:
Semiconductor fabrication methods to forma of via contacts in DSL (dual stress liner) semiconductor devices are provided, in which improved etching process flows are implemented to enable etching of via contact openings through overlapped and non-overlapped regions of the dual stress liner structure to expose underlying salicided contacts and other device contacts, while mitigating or eliminating defect mechanisms such as over etching of contact regions underlying non-overlapped regions of the DSL.
Public/Granted literature
- US20090017630A1 Methods For Forming Contacts For Dual Stress Liner CMOS Semiconductor Devices Public/Granted day:2009-01-15
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