A semiconductor memory device performing an erase operation using an erase gate and a method of manufacturing the same are provided. The memory device may include a charge trap layer storing a first charge transfer medium having a first polarity and at least one erase gate. The at least one erase gate may be formed below the charge trap layer. A second charge transfer medium, which has a second polarity opposite to the first polarity, may be stored in the at least one erase gate. During the erase operation, the second charge transfer medium migrates to the charge trap layer causing the first charge transfer medium to combine with the second charge transfer medium.