Invention Grant
- Patent Title: Fabrication method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US12853360Application Date: 2010-08-10
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Publication No.: US07901958B2Publication Date: 2011-03-08
- Inventor: Masayoshi Okamoto , Yoshiaki Hasegawa , Yasuhiro Motoyama , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Ryuji Shibata , Yasunori Narizuka , Akira Yabushita , Toshiyuki Majima
- Applicant: Masayoshi Okamoto , Yoshiaki Hasegawa , Yasuhiro Motoyama , Hideyuki Matsumoto , Shingo Yorisaki , Akio Hasebe , Ryuji Shibata , Yasunori Narizuka , Akira Yabushita , Toshiyuki Majima
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2003-371515 20031031
- Main IPC: G01R31/26
- IPC: G01R31/26 ; H01L21/66
Abstract:
To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.
Public/Granted literature
- US20100304510A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2010-12-02
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