Invention Grant
US08034677B2 Integrated method for forming high-k metal gate FinFET devices
有权
用于形成高k金属栅极FinFET器件的集成方法
- Patent Title: Integrated method for forming high-k metal gate FinFET devices
- Patent Title (中): 用于形成高k金属栅极FinFET器件的集成方法
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Application No.: US12712594Application Date: 2010-02-25
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Publication No.: US08034677B2Publication Date: 2011-10-11
- Inventor: Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
- Applicant: Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
Public/Granted literature
- US20110207279A1 INTEGRATED METHOD FOR FORMING HIGH-K METAL GATE FINFET DEVICES Public/Granted day:2011-08-25
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