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公开(公告)号：US08796095B2
公开(公告)日：2014-08-05
申请号：US13241014
申请日：2011-09-22
Applicant: Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
Inventor： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC: H01L21/336
CPC classification number: H01L29/66795 , H01L29/66803
Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。
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公开(公告)号：US20100238159A1
公开(公告)日：2010-09-23
申请号：US12726931
申请日：2010-03-18
Applicant: Wen-Hsia KUNG , Tzuo-Bo LIN , Chia-Lung HUNG , Yu-Pin CHOU
Inventor： Wen-Hsia KUNG , Tzuo-Bo LIN , Chia-Lung HUNG , Yu-Pin CHOU
CPC classification number: H03K5/151 , H03K19/0008
Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.
Abstract translation: 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时，控制电路接收源信号并产生对应于第一模式的控制信号，并且当源信号符合第二预定义状态时，控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时，差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时，差分信号驱动器输出非差分信号输出。
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公开(公告)号：US20100188574A1
公开(公告)日：2010-07-29
申请号：US12692389
申请日：2010-01-22
Applicant: Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
Inventor： Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
CPC classification number: H04N7/0105 , H04N7/0132
Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。
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公开(公告)号：US08471859B2
公开(公告)日：2013-06-25
申请号：US12692389
申请日：2010-01-22
Applicant: Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
Inventor： Chia-Lung Hung , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
CPC classification number: H04N7/0105 , H04N7/0132
Abstract: A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
Abstract translation: 用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。 输入像素时钟不等于输出像素时钟。 帧写入控制器根据输入DE和输出DE生成写许可信号。 缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。 缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。
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公开(公告)号：US20120015493A1
公开(公告)日：2012-01-19
申请号：US13241014
申请日：2011-09-22
Applicant: Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
Inventor： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC: H01L21/336
CPC classification number: H01L29/66795 , H01L29/66803
Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。
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Patent Agency Ranking
公开(公告)号：US20080290375A1
公开(公告)日：2008-11-27
申请号：US12127265
申请日：2008-05-27
Applicant: Hsien Chun Chang , Chia Lung Hung , Tsung Chi Lin , Tzuo Bo Lin
Inventor： Hsien Chun Chang , Chia Lung Hung , Tsung Chi Lin , Tzuo Bo Lin
IPC: H01L27/10
CPC classification number: H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/32145 , H01L2224/48145 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/10161 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
Abstract: The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package.
Abstract translation: 本发明提供适用于各种封装模式的集成电路。 该集成电路包括：核心电路，多个焊盘和选择电路。 选择电路耦合在核心电路和焊盘之间，用于基于控制信号确定核心电路和焊盘之间的连接状态。 当控制信号提供第一值时，核心电路和焊盘将处于第一连接状态，并且集成电路将被应用于单模封装。 然而，当控制信号提供第二值时，核心电路和焊盘将处于第二连接状态，并且集成电路将被应用于多管芯封装。
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公开(公告)号：US08034677B2
公开(公告)日：2011-10-11
申请号：US12712594
申请日：2010-02-25
Applicant: Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
Inventor： Chia-Pin Lin , Wen-Sheh Huang , Tian-Choy Gan , Chia-Lung Hung , Hsien-Chin Lin , Shyue-Shyh Lin
IPC: H01L21/336
CPC classification number: H01L29/66795 , H01L29/66803
Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiN, or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。 第一氮化物膜可以是SiN或SiCNx，并且第二氮化物膜是在H3PO4中的低湿蚀刻速率的SiCNx和稀释的HF酸。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。
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公开(公告)号：US20110207279A1
公开(公告)日：2011-08-25
申请号：US12712594
申请日：2010-02-25
Applicant: Chia-Pin LIN , Wen-Sheh HUANG , Tian-Choy GAN , Chia-Lung HUNG , Hsien-Chin LIN , Shyue-Shyh LIN
Inventor： Chia-Pin LIN , Wen-Sheh HUANG , Tian-Choy GAN , Chia-Lung HUNG , Hsien-Chin LIN , Shyue-Shyh LIN
IPC: H01L21/336
CPC classification number: H01L29/66795 , H01L29/66803
Abstract: Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations such as an LDD or a PKT implant, are carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx with a low wet etch rate in H3PO4 and dilute HF acid. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.
Abstract translation: 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 在两个氮化物膜沉积操作之间进行诸如LDD或PKT注入的植入操作。 第一氮化物膜可以是SiNx或SiCNx，并且第二氮化物膜是SiCNx，在H 3 PO 4中具有低湿蚀刻速率和稀释的HF酸。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。
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公开(公告)号：US08513708B2
公开(公告)日：2013-08-20
申请号：US12127265
申请日：2008-05-27
Applicant: Hsien Chun Chang , Chia Lung Hung , Tsung Chi Lin , Tzuo Bo Lin
Inventor： Hsien Chun Chang , Chia Lung Hung , Tsung Chi Lin , Tzuo Bo Lin
IPC: H01L27/10
CPC classification number: H01L23/50 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/32145 , H01L2224/48145 , H01L2224/48247 , H01L2224/49171 , H01L2224/49175 , H01L2224/85399 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/10161 , H01L2924/14 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
Abstract: The present invention provides an integrated circuit suitable for various packaging modes. This integrated circuit includes: a core circuit, a plurality of pads, and a selection circuit. The selection circuit is coupled between the core circuit and the pads for determining the connection state between the core circuit and the pads based on a control signal. When the control signal provides a first value, the core circuit and the pads will be in a first connection state, and the integrated circuit will be applied with a single-die package. However, when the control signal provides a second value, the core circuit and the pads will be in the second connection state, and the integrated circuit will be applied with a multi-die package.
Abstract translation: 本发明提供适用于各种封装模式的集成电路。 该集成电路包括：核心电路，多个焊盘以及选择电路。 选择电路耦合在核心电路和焊盘之间，用于基于控制信号确定核心电路和焊盘之间的连接状态。 当控制信号提供第一值时，核心电路和焊盘将处于第一连接状态，并且集成电路将被应用于单模封装。 然而，当控制信号提供第二值时，核心电路和焊盘将处于第二连接状态，并且集成电路将被应用于多管芯封装。
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公开(公告)号：US08362804B2
公开(公告)日：2013-01-29
申请号：US12726931
申请日：2010-03-18
Applicant: Wen-Hsia Kung , Tzuo-Bo Lin , Chia-Lung Hung , Yu-Pin Chou
Inventor： Wen-Hsia Kung , Tzuo-Bo Lin , Chia-Lung Hung , Yu-Pin Chou
IPC: H03K19/0175
CPC classification number: H03K5/151 , H03K19/0008
Abstract: A differential signal generating device includes a control circuit and a differential signal driver receiving a single-ended signal. The control circuit receives a source signal and generates a control signal corresponding to a first mode when the source signal conforms with a first pre-defined state, and corresponding to a second mode when the source signal conforms with a second pre-defined state. Variations of the source signal are related to signal content of the single-ended signal. The differential signal driver is coupled to the control unit for receiving the control signal therefrom. The differential signal driver outputs a differential signal output according to the single-ended signal when the control signal corresponds to the first mode. The differential signal driver outputs a non-differential signal output when the control signal corresponds to the second mode.
Abstract translation: 差分信号发生装置包括控制电路和接收单端信号的差分信号驱动器。 当源信号符合第一预定义状态时，控制电路接收源信号并产生对应于第一模式的控制信号，并且当源信号符合第二预定义状态时，控制电路对应于第二模式。 源信号的变化与单端信号的信号内容有关。 差分信号驱动器耦合到控制单元以从其接收控制信号。 当控制信号对应于第一模式时，差分信号驱动器根据单端信号输出差分信号。 当控制信号对应于第二模式时，差分信号驱动器输出非差分信号输出。
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