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    Method of making a finFET, and finFET formed by the method
    1.
    发明授权
    Method of making a finFET, and finFET formed by the method 有权
    制造finFET的方法和通过该方法形成的finFET

    公开(公告)号：US09312179B2

    公开(公告)日：2016-04-12

    申请号：US12725554

    申请日：2010-03-17

    申请人： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    发明人： Chia-Pin Lin ,  Chien-Tai Chan ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

    CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    摘要： A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

    摘要翻译： 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

    Integrated method for forming metal gate FinFET devices
    2.
    发明授权
    Integrated method for forming metal gate FinFET devices 有权
    用于形成金属栅极FinFET器件的集成方法

    公开(公告)号：US08796095B2

    公开(公告)日：2014-08-05

    申请号：US13241014

    申请日：2011-09-22

    申请人： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    发明人： Chia-Pin Lin ,  Wen-Sheh Huang ,  Tian-Choy Gan ,  Chia-Lung Hung ,  Hsien-Chin Lin ,  Shyue-Shyh Lin

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66795 ,  H01L29/66803

    摘要： Provided is a high-k metal gate structure formed over a semiconductor fin. A nitride layer is formed over the gate structure and the semiconductor fin, using two separate deposition operations, the first forming a very thin nitride film. Implantation operations may be carried out in between the two nitride film deposition operations. The first nitride film may be SiNx or SiCNx and the second nitride film is SiCNx. The nitride films may be combined to form low wet etch rate spacers enabling further processing operations to be carried out without damaging underlying structures and without requiring the formation of further dummy spacers. Further processing operations include epitaxial silicon/SiGe processing sequences and source/drain implanting operations carried out with the low etch rate spacers intact.

    摘要翻译： 提供了形成在半导体鳍上的高k金属栅极结构。 在栅极结构和半导体鳍片上形成氮化物层，使用两个单独的沉积操作，首先形成非常薄的氮化物膜。 植入操作可以在两个氮化物膜沉积操作之间进行。 第一氮化物膜可以是SiNx或SiCNx，第二氮化物膜是SiCNx。 可以将氮化物膜组合以形成低湿蚀刻速率间隔物，使得能够进行进一步的处理操作而不损坏下面的结构，而不需要形成另外的虚设间隔物。 进一步的处理操作包括外延硅/ SiGe处理序列和用低蚀刻速率间隔物完整地进行的源极/漏极注入操作。

    METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD
    6.
    发明申请
    METHOD OF MAKING A FINFET, AND FINFET FORMED BY THE METHOD 有权
    制造FINFET的方法和由该方法形成的FINFET

    公开(公告)号：US20110227162A1

    公开(公告)日：2011-09-22

    申请号：US12725554

    申请日：2010-03-17

    申请人： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    发明人： Chia-Pin LIN ,  Chien-Tai CHAN ,  Hsien-Chin LIN ,  Shyue-Shyh LIN

    IPC分类号： H01L27/08 ,  H01L21/336 ,  H01L21/8234 ,  H01L29/78

    CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

    摘要： A method includes forming first and second fins of a finFET extending above a semiconductor substrate, with a shallow trench isolation (STI) region in between, and a distance between a top surface of the STI region and top surfaces of the first and second fins. First and second fin extensions are provided on top and side surfaces of the first and second fins above the top surface of the STI region. Material is removed from the STI region, to increase the distance between the top surface of the STI region and top surfaces of the first and second fins. A conformal stressor dielectric material is deposited over the fins and STI region. The conformal dielectric stressor material is reflowed, to flow into a space between the first and second fins above a top surface of the STI region, to apply stress to a channel of the finFET.

    摘要翻译： 一种方法包括形成在半导体衬底之上延伸的finFET的第一和第二鳍片，其间具有浅沟槽隔离（STI）区域，以及STI区域的顶表面与第一鳍片和第二鳍片的顶表面之间的距离。 第一和第二鳍片延伸部分设置在STI区域顶表面上方的第一和第二鳍片的顶表面和侧表面上。 从STI区域去除材料，以增加STI区域的顶表面与第一和第二鳍片的顶表面之间的距离。 保形应力源电介质材料沉积在鳍片和STI区域上。 共形介电应力材料被回流，以流入STI区域的顶表面之上的第一和第二鳍片之间的空间，以向finFET的沟道施加应力。

    Magnetic memory array
    7.
    发明授权
    Magnetic memory array 有权
    磁存储阵列

    公开(公告)号：US07349234B2

    公开(公告)日：2008-03-25

    申请号：US11119052

    申请日：2005-04-29

    申请人： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

    发明人： Yuan-Ching Peng ,  Shyue-Shyh Lin ,  Wei-Ming Chen

    IPC分类号： G11C5/08

    CPC分类号： G11C11/15 ,  G11C5/063

    摘要： A magnetic random access memory (MRAM) device disclosed herein includes an array of magnetic memory cells having magnetoresistive (MR) stacks. The MRAM array also includes a series of bit lines and word lines coupled to the MR stacks. The array layout provides for reduced crosstalk between neighboring memory cells by increasing a distance between neighboring MR stacks along a common conductor without increasing the overall layout area of the MRAM array. Several embodiments are disclosed where neighboring MR stacks are offset such that the MR stacks are staggered. For example, groups of MR stacks coupled to a common word line or to a common bit line can be staggered. The staggered layout provides for increased distance between neighboring MR stacks for a given MRAM array area, thereby resulting in a reduction of crosstalk, for example during write operations.

    摘要翻译： 本文公开的磁性随机存取存储器（MRAM）装置包括具有磁阻（MR）堆叠的磁存储器单元阵列。 MRAM阵列还包括耦合到MR堆叠的一系列位线和字线。 阵列布局通过增加沿着公共导体的相邻MR堆叠之间的距离而不增加MRAM阵列的总体布局面积来提供相邻存储器单元之间减少的串扰。 公开了几个实施例，其中相邻MR堆叠被偏移，使得MR堆叠交错。 例如，耦合到公共字线或公共位线的MR堆叠组可以交错。 交错布局提供了对于给定MRAM阵列区域的相邻MR堆叠之间的距离增加，从而导致例如在写入操作期间串扰的减少。

    Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer
    8.
    发明授权
    Use of fluorine implantation to form a charge balanced nitrided gate dielectric layer 失效

    公开(公告)号：US06825133B2

    公开(公告)日：2004-11-30

    申请号：US10351158

    申请日：2003-01-22

    申请人： Mo-Chiun Yu ,  Shyue-Shyh Lin

    发明人： Mo-Chiun Yu ,  Shyue-Shyh Lin

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/513 ,  H01L29/518

    摘要： A method of forming a charge balanced, silicon dioxide layer gate insulator layer on a semiconductor substrate, with reduced leakage obtained via nitrogen treatments, has been developed. Prior to thermal growth of a silicon dioxide gate insulator layer, negatively charged fluorine ions are implanted into a top portion of a semiconductor substrate. The thermal oxidation procedure results in the growth of a silicon dioxide layer with incorporated, negatively charged fluorine ions. Subsequent nitrogen treatments, used to reduce gate insulator leakage, result in generation of positive charge in the exposed silicon dioxide layer, compensating the negatively charged fluorine ions and resulting in the desired charge balanced, silicon dioxide gate insulator layer. Nitrogen treatments can be a plasma nitridization procedure, or anneal procedure, both performed in a nitrogen containing ambient, or the positive charge can be generated in the underlying silicon dioxide gate insulator layer via deposition of an overlying silicon nitride layer.