Invention Grant
- Patent Title: Method of fabricating semiconductor integrated circuit device
- Patent Title (中): 制造半导体集成电路器件的方法
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Application No.: US12492276Application Date: 2009-06-26
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Publication No.: US08034715B2Publication Date: 2011-10-11
- Inventor: Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- Applicant: Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L21/8238
Abstract:
A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
Public/Granted literature
- US20090263943A1 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2009-10-22
Information query
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