Invention Grant
- Patent Title: Methods of forming a non-volatile resistive oxide memory array
- Patent Title (中): 形成非易失性电阻氧化物存储器阵列的方法
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Application No.: US12141559Application Date: 2008-06-18
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Publication No.: US08114468B2Publication Date: 2012-02-14
- Inventor: Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
- Applicant: Gurtej Sandhu , John Smythe , Bhaskar Srinivasan
- Applicant Address: US ID Boise
- Assignee: Boise Technology, Inc.
- Current Assignee: Boise Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: B05D5/12
- IPC: B05D5/12 ; B28B19/00 ; B29B15/00 ; C23C18/00 ; C23C20/00 ; C23C24/00 ; C23C26/00 ; C23C28/00 ; C23C30/00 ; H01C17/06 ; H05K3/00 ; H01L47/00 ; H01L29/08 ; H01L35/24 ; H01L51/00 ; H01L29/02 ; H01L21/00 ; H01L21/16 ; H01L21/20 ; H01L21/36 ; G11C11/00

Abstract:
A method of forming a non-volatile resistive oxide memory array includes forming a plurality of one of conductive word lines or conductive bit lines over a substrate. Metal oxide-comprising material is formed over the plurality of said one of the word lines or bit lines. A series of elongated trenches is provided over the plurality of said one of the word lines or bit lines. A plurality of self-assembled block copolymer lines is formed within individual of the trenches in registered alignment with and between the trench sidewalls. A plurality of the other of conductive word lines or conductive bit lines is provided from said plurality of self-assembled block copolymer lines to form individually programmable junctions comprising said metal oxide-comprising material where the word lines and bit lines cross one another.
Public/Granted literature
- US20090317540A1 Methods Of Forming A Non-Volatile Resistive Oxide Memory Array Public/Granted day:2009-12-24
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