Invention Grant
US08193567B2 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
有权
用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
- Patent Title: Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
- Patent Title (中): 用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
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Application No.: US12333248Application Date: 2008-12-11
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Publication No.: US08193567B2Publication Date: 2012-06-05
- Inventor: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
- Applicant: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Blakely, Sokoloff, Taylor & Zafman LLP
- Main IPC: H01L29/76
- IPC: H01L29/76
Abstract:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
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Information query
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