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1.发明申请PROCESS FOR INTEGRATING PLANAR AND NON-PLANAR CMOS TRANSISTORS ON A BULK SUBSTRATE AND ARTICLE MADE THEREBY 有权在大容量基板上集成平面和非平面CMOS晶体管的过程及其制造公开(公告)号：US20090090976A1
公开(公告)日：2009-04-09
申请号：US12333248
申请日：2008-12-11
申请人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/78
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译： 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。
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2.发明授权Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺公开(公告)号：US08193567B2
公开(公告)日：2012-06-05
申请号：US12333248
申请日：2008-12-11
申请人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/76
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译： 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。
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3.发明授权Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby 有权用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺公开(公告)号：US07479421B2
公开(公告)日：2009-01-20
申请号：US11238444
申请日：2005-09-28
申请人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
发明人： Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L21/8234
CPC分类号： H01L21/823828 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L29/1037 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
摘要翻译： 一种能够将平面和非平面晶体管集成到体半导体衬底上的工艺，其中所有晶体管的沟道可在连续的宽度范围内定义。
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公开(公告)号：US07858481B2
公开(公告)日：2010-12-28
申请号：US11154138
申请日：2005-06-15
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。
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公开(公告)号：US09337307B2
公开(公告)日：2016-05-10
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
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公开(公告)号：US20110062520A1
公开(公告)日：2011-03-17
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/786
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。
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7.发明授权公开(公告)号：US07176090B2
公开(公告)日：2007-02-13
申请号：US10936114
申请日：2004-09-07
申请人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Brian S. Doyle , Robert S. Chau
发明人： Justin K. Brask , Jack Kavalieros , Mark L. Doczy , Matthew V. Metz , Suman Datta , Uday Shah , Brian S. Doyle , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L21/82385 , H01L21/28114 , H01L21/30608 , H01L21/823828 , H01L29/42376 , H01L29/66545 , Y10S438/926
摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer and a sacrificial structure that comprises a first layer and a second layer, such that the second layer is formed on the first layer and is wider than the first layer. After the sacrificial structure is removed to generate a trench, a metal gate electrode is formed within the trench.
摘要翻译： 描述制造半导体器件的方法。 该方法包括在衬底上形成介电层和包括第一层和第二层的牺牲结构，使得第二层形成在第一层上并且比第一层更宽。 在除去牺牲结构以产生沟槽之后，在沟槽内形成金属栅电极。
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公开(公告)号：US07390947B2
公开(公告)日：2008-06-24
申请号：US11037512
申请日：2005-01-18
申请人： Amlan Majumdar , Justin K. Brask , Marko Radosavljevic , Suman Datta , Brian S. Doyle , Mark L. Doczy , Jack Kavalieros , Matthew V. Metz , Robert S. Chau , Uday Shah , James Blackwell
发明人： Amlan Majumdar , Justin K. Brask , Marko Radosavljevic , Suman Datta , Brian S. Doyle , Mark L. Doczy , Jack Kavalieros , Matthew V. Metz , Robert S. Chau , Uday Shah , James Blackwell
IPC分类号： H01L29/12
CPC分类号： B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/1606 , H01L51/0048 , H01L51/0052 , H01L51/0541 , H01L51/0545 , Y10S977/701 , Y10S977/938
摘要： A nanotube transistor, such as a carbon nanotube transistor, may be formed with a top gate electrode and a spaced source and drain. Conduction along the transistor from source to drain is controlled by the gate electrode. Underlying the gate electrode are at least two nanotubes. In some embodiments, the substrate may act as a back gate.
摘要翻译： 诸如碳纳米管晶体管的纳米管晶体管可以形成有顶栅电极和间隔开的源极和漏极。 沿晶体管从源极到漏极的导通由栅电极控制。 栅电极底部至少有两个纳米管。 在一些实施例中，衬底可用作背栅。
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公开(公告)号：US07989280B2
公开(公告)日：2011-08-02
申请号：US12338839
申请日：2008-12-18
申请人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
发明人： Justin K. Brask , Suman Datta , Mark L. Doczy , James M. Blackwell , Matthew V. Metz , Jack T. Kavalieros , Robert S. Chau
IPC分类号： H01L21/336
CPC分类号： H01L21/314 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28008 , H01L21/3141 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/495 , H01L29/513 , H01L29/517 , H01L29/66462 , H01L29/7784
摘要： A Group III-V Semiconductor device and method of fabrication is described. A high-k dielectric is interfaced to a confinement region by a chalcogenide region.
摘要翻译： 描述了III-V族半导体器件及其制造方法。 高k电介质通过硫族化物区域连接到约束区域。
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公开(公告)号：US20140291615A1
公开(公告)日：2014-10-02
申请号：US14302371
申请日：2014-06-11
申请人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
发明人： Suman Datta , Mantu K. Hudait , Mark L. Doczy , Jack T. Kavalieros , Majumdar Amian , Justin K. Brask , Been-Yih Jin , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L27/092 , H01L29/15
CPC分类号： H01L29/7784 , H01L21/02178 , H01L21/02381 , H01L21/02546 , H01L21/823807 , H01L21/823885 , H01L21/8252 , H01L27/0605 , H01L27/092 , H01L29/1054 , H01L29/122 , H01L29/15 , H01L29/157 , H01L29/205 , H01L29/41783 , H01L29/42364 , H01L29/42376 , H01L29/517 , H01L29/66462 , H01L29/66522 , H01L29/7783
摘要： A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS transistors are formed on a substrate.
摘要翻译： CMOS器件包括具有第一量子阱结构的PMOS晶体管和具有第二量子阱结构的NMOS器件。 PMOS和NMOS晶体管形成在衬底上。
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