发明授权
US08193567B2 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
有权
用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
- 专利标题: Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
- 专利标题(中): 用于将体积衬底上的平面和非平面CMOS晶体管和由此制成的制品集成的工艺
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申请号: US12333248申请日: 2008-12-11
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公开(公告)号: US08193567B2公开(公告)日: 2012-06-05
- 发明人: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
- 申请人: Jack T. Kavalieros , Justin K. Brask , Brian S. Doyle , Uday Shah , Suman Datta , Mark L. Doczy , Matthew V. Metz , Robert S. Chau
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: H01L29/76
- IPC分类号: H01L29/76
摘要:
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable over a continuous range of widths.
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