Invention Grant
US08207568B2 Process for single and multiple level metal-insulator-metal integration with a single mask
有权
单层和多层金属绝缘体金属与单一掩模集成的工艺
- Patent Title: Process for single and multiple level metal-insulator-metal integration with a single mask
- Patent Title (中): 单层和多层金属绝缘体金属与单一掩模集成的工艺
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Application No.: US11162661Application Date: 2005-09-19
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Publication No.: US08207568B2Publication Date: 2012-06-26
- Inventor: Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
- Applicant: Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Anthony Canale
- Main IPC: H01L29/92
- IPC: H01L29/92

Abstract:
Method of fabricating a MIM capacitor and MIM capacitor. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
Public/Granted literature
- US20070065966A1 PROCESS FOR SINGLE AND MULTIPLE LEVEL METAL-INSULATOR-METAL INTEGRATION WITH A SINGLE MASK Public/Granted day:2007-03-22
Information query
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