Invention Grant
- Patent Title: Via/contact and damascene structures and manufacturing methods thereof
- Patent Title (中): 通孔/接触和镶嵌结构及其制造方法
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Application No.: US11680981Application Date: 2007-03-01
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Publication No.: US08247322B2Publication Date: 2012-08-21
- Inventor: Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
- Applicant: Shih-Chieh Chang , Ying-Lang Wang , Kei-Wei Chen , Jung-Chih Tsao , Yu-Sheng Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/44
- IPC: H01L21/44

Abstract:
A method for forming a semiconductor structure includes forming a dielectric layer over a substrate. A first non-conductive barrier layer is formed over the dielectric layer. At least one opening is formed through the first non-conductive barrier layer and within the dielectric layer. A second non-conductive barrier layer is formed over the first non-conductive barrier layer and within the opening. At least a portion of the second non-conductive barrier layer is removed, thereby at least partially exposing a top surface of the first non-conductive barrier layer and a bottom surface of the opening, with the second non-conductive barrier layer remaining on sidewalls of the opening. A seed layer and conductive layer is then formed and a single polishing operation removes the seed layer and conductive layer.
Public/Granted literature
- US20080211106A1 VIA/CONTACT AND DAMASCENE STRUCTURES AND MANUFACTURING METHODS THEREOF Public/Granted day:2008-09-04
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