发明授权
US08343868B2 Device and methodology for reducing effective dielectric constant in semiconductor devices
有权
用于降低半导体器件中有效介电常数的器件和方法
- 专利标题： Device and methodology for reducing effective dielectric constant in semiconductor devices
- 专利标题（中）： 用于降低半导体器件中有效介电常数的器件和方法
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申请号： US13005201申请日： 2011-01-12
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公开(公告)号： US08343868B2公开(公告)日： 2013-01-01
- 发明人: Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
- 申请人： Daniel C. Edelstein , Matthew E. Colburn , Edward C. Cooney, III , Timothy J. Dalton , John A. Fitzsimmons , Jeffrey P. Gambino , Elbert E. Huang , Michael W. Lane , Vincent J. McGahay , Lee M. Nicholson , Satyanarayana V. Nitta , Sampath Purushothaman , Sujatha Sankaran , Thomas M. Shaw , Andrew H. Simon , Anthony K. Stamper
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Roberts, Mlotkowski, Safran & Cole, P.C.
- 代理商 Ian MacKinnon
- 主分类号： H01L21/00
- IPC分类号： H01L21/00
摘要：
Method of manufacturing a structure which includes the steps of providing a structure having an insulator layer with at least one interconnect, forming a sub lithographic template mask over the insulator layer, and selectively etching the insulator layer through the sub lithographic template mask to form sub lithographic features spanning to a sidewall of the plurality of interconnects.
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