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US08392728B2 Reducing idle leakage power in an IC 有权
降低IC中的空闲泄漏功率

Reducing idle leakage power in an IC
摘要:
A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
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