Invention Grant
- Patent Title: Reducing idle leakage power in an IC
- Patent Title (中): 降低IC中的空闲泄漏功率
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Application No.: US11615749Application Date: 2006-12-22
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Publication No.: US08392728B2Publication Date: 2013-03-05
- Inventor: Lance Hacking , Belliappa Kuttanna , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
- Applicant: Lance Hacking , Belliappa Kuttanna , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Jordan IP Law, LLC
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/32
Abstract:
A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
Public/Granted literature
- US20080155280A1 REDUCING IDLE LEAKAGE POWER IN AN IC Public/Granted day:2008-06-26
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