Invention Grant
US08451970B2 Variable delay circuit and delay-locked loop including the same 有权
可变延迟电路和延迟锁定环路包括相同

Variable delay circuit and delay-locked loop including the same
Abstract:
The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
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