Invention Grant
- Patent Title: Variable delay circuit and delay-locked loop including the same
- Patent Title (中): 可变延迟电路和延迟锁定环路包括相同
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Application No.: US13035093Application Date: 2011-02-25
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Publication No.: US08451970B2Publication Date: 2013-05-28
- Inventor: Chul Woo Kim , Young Ho Kwak
- Applicant: Chul Woo Kim , Young Ho Kwak
- Applicant Address: KR Seoul
- Assignee: Korea University Research and Business Foundation
- Current Assignee: Korea University Research and Business Foundation
- Current Assignee Address: KR Seoul
- Agency: Pearne & Gordon LLP
- Priority: KR10-2010-0020321 20100308
- Main IPC: H03D3/24
- IPC: H03D3/24 ; H04L7/00 ; H04L25/40 ; H03L7/06 ; H03L7/00

Abstract:
The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.
Public/Granted literature
- US20110216864A1 VARIABLE DELAY CIRCUIT AND DELAY-LOCKED LOOP INCLUDING THE SAME Public/Granted day:2011-09-08
Information query
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