发明授权
US08607000B2 Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU
有权
通过根据CPU所需的字节优化分配命令的大小和顺序，实现高效的缓存分配
- 专利标题： Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU
- 专利标题（中）： 通过根据CPU所需的字节优化分配命令的大小和顺序，实现高效的缓存分配
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申请号： US13243411申请日： 2011-09-23
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公开(公告)号： US08607000B2公开(公告)日： 2013-12-10
- 发明人: Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
- 申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Robert D. Marshall, Jr.; Wade James Brady, III; Frederick J. Telecky, Jr.
- 主分类号： G06F12/04
- IPC分类号： G06F12/04 ; G06F12/12
摘要：
This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
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