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1.发明授权Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU 有权通过根据CPU所需的字节优化分配命令的大小和顺序，实现高效的缓存分配公开(公告)号：US08607000B2
公开(公告)日：2013-12-10
申请号：US13243411
申请日：2011-09-23
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
摘要翻译： 本发明是一种具有多级缓存系统的数据处理系统。 多级缓存系统至少包括第一级缓存和第二级高速缓存。 在所述至少一个第一级高速缓存和所述第二级高速缓存中的高速缓存未命中时，所述数据处理系统在所述第二级高速缓存内驱逐并分配高速缓存行。 数据处理系统从未命中地址确定请求是否落在所分配的高速缓存行的低一半或高一半内。 数据处理系统首先从缺失半高速缓存行的外部存储器请求数据。 当接收数据被提供给至少一个第一级高速缓存和CPU时。 数据处理系统然后从第二级高速缓存行的另一半请求来自外部存储器的数据。
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2.发明申请OPTIMIZING TAG FORWARDING IN A TWO LEVEL CACHE SYSTEM FROM LEVEL ONE TO LEVER TWO CONTROLLERS FOR CACHE COHERENCE PROTOCOL FOR DIRECT MEMORY ACCESS TRANSFERS 有权优化标签在两级高速缓存系统中从一级到两级控制器，用于直接存储器访问传输的高速缓存协议协议公开(公告)号：US20120191916A1
公开(公告)日：2012-07-26
申请号：US13245206
申请日：2011-09-26
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
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3.发明申请Efficient Cache Allocation by Optimizing Size and Order of Allocate Commands Based on Bytes Required by CPU 有权通过优化基于CPU所需字节的分配命令的大小和顺序来实现高效缓存分配公开(公告)号：US20120198160A1
公开(公告)日：2012-08-02
申请号：US13243411
申请日：2011-09-23
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
摘要翻译： 本发明是一种具有多级缓存系统的数据处理系统。 多级缓存系统至少包括第一级缓存和第二级高速缓存。 在所述至少一个第一级高速缓存和所述第二级高速缓存中的高速缓存未命中时，所述数据处理系统在所述第二级高速缓存内驱逐并分配高速缓存行。 数据处理系统从未命中地址确定请求是否落在所分配的高速缓存行的低一半或高一半内。 数据处理系统首先从缺失半高速缓存行的外部存储器请求数据。 当接收数据被提供给至少一个第一级高速缓存和CPU时。 数据处理系统然后从第二级高速缓存行的另一半请求来自外部存储器的数据。
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公开(公告)号：US08560896B2
公开(公告)日：2013-10-15
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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公开(公告)号：US20120198272A1
公开(公告)日：2012-08-02
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/16
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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6.发明授权Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme 有权用于使用双存储器方案的多级缓存系统中的软错误检测，校正和报告的鲁棒汉明码实现公开(公告)号：US08904260B2
公开(公告)日：2014-12-02
申请号：US13243370
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
IPC分类号： H03M13/00 , G11C29/00 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
摘要翻译： 本发明是一种具有两个存储体的存储器系统，其可以存储和调用具有两种不同尺寸的数据的存储器错误检测和校正。 为单独的奇偶校验生成器形成相应存储体的奇偶校验位。 用于读取单独的奇偶检测器/发生器对单独存储体的数据进行操作。
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7.发明授权Optimizing tag forwarding in a two level cache system from level one to lever two controllers for cache coherence protocol for direct memory access transfers 有权优化从一级的二级缓存系统中的标签转发，以便两个控制器用于直接内存访问传输的缓存一致性协议公开(公告)号：US08656105B2
公开(公告)日：2014-02-18
申请号：US13245206
申请日：2011-09-26
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Jonathan (Son) Hung Tran
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
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8.发明授权Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirty 有权在一级数据缓存和行中引起的二级组合高速缓存/ SRAM的DMA写入的性能和电源改进是有效和脏的公开(公告)号：US09075744B2
公开(公告)日：2015-07-07
申请号：US13245183
申请日：2011-09-26
申请人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
发明人： Jonathan (Son) Hung Tran , Raguram Damodaran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak
IPC分类号： G06F12/08 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention optimizes DMA writes to directly addressable level two memory that is cached in level one and the line is valid and dirty. When the level two controller detects that a line is valid and dirty in level one, the level two memory need not update its copy of the data. Level one memory will replace the level two copy with a victim writeback at a future time. Thus the level two memory need not store write a copy. This limits the number of DMA writes to level two directly addressable memory and thus improves performance and minimizes dynamic power. This also frees the level two memory for other master/requestors.
摘要翻译： 本发明将DMA写入优化为直接可寻址的二级存储器，该存储器缓存在一级，并且该行是有效和脏的。 当二级控制器检测到一级线路有效且脏一级时，二级存储器不需要更新其数据副本。 一级记忆将在将来的时候用受害者回写替代第二级副本。 因此，二级内存不需要存储写入副本。 这将DMA写入次数限制在二级可直接寻址的存储器中，从而提高性能并最大限度地减少动态功耗。 这也释放了其他主/请求者的二级内存。
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公开(公告)号：US20120290755A1
公开(公告)日：2012-11-15
申请号：US13230131
申请日：2011-09-12
申请人： Abhijeet Ashok Chachad , Raguram Damodaran , Ramakrishnan Venkatasubramanian , Joseph Raymond Michael Zbiciak
发明人： Abhijeet Ashok Chachad , Raguram Damodaran , Ramakrishnan Venkatasubramanian , Joseph Raymond Michael Zbiciak
IPC分类号： G06F13/14
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A queuing requester for access to a memory system. Transaction requests received from two or more requestors access to the memory system. Each transaction request includes an associated priority value. A request queue is formed in the queuing requester. Each transaction request includes an associated priority value. A highest priority value of all pending transaction requests within the request queue is determined. An elevated priority value is selected when the highest priority value is higher than the priority value of an oldest transaction request in the request queue; otherwise the priority value of the oldest transaction request is selected. The oldest transaction request in the request queue with the selected priority value is then provided to the memory system. An arbitration contest with other requesters for access to the memory system uses the selected priority value.
摘要翻译： 访问内存系统的排队请求者。 从两个或多个请求者接收到的访问存储器系统的事务请求。 每个交易请求都包含一个关联的优先级值。 在排队请求者中形成请求队列。 每个交易请求都包含一个关联的优先级值。 确定请求队列中所有待处理事务请求的最高优先级值。 当最高优先级值高于请求队列中最早的事务请求的优先级值时，选择提升的优先级值; 否则选择最旧的事务请求的优先级值。 然后，将具有所选优先级值的请求队列中的最早的事务请求提供给存储系统。 与其他请求者的访问内存系统的仲裁比赛使用所选的优先级值。
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10.发明申请Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme 有权使用双银行内存方案的多级缓存系统中的软错误检测，更正和报告的强大汉明码实现公开(公告)号：US20120192027A1
公开(公告)日：2012-07-26
申请号：US13243370
申请日：2011-09-23
申请人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
发明人： Jonathan (Son) Hung Tran , Abhijeet Ashok Chachad , Joseph Raymond Michael Zbiciak , Krishna Chaithanya Gurram
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
摘要翻译： 本发明是一种具有两个存储体的存储器系统，其可以存储和调用具有两种不同尺寸的数据的存储器错误检测和校正。 为单独的奇偶校验生成器形成相应存储体的奇偶校验位。 用于读取单独的奇偶检测器/发生器对单独存储体的数据进行操作。
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