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    SYSTEM AND METHOD OF OPTIMIZED USER COHERENCE FOR A CACHE BLOCK WITH SPARSE DIRTY LINES
    2.
    发明申请
    SYSTEM AND METHOD OF OPTIMIZED USER COHERENCE FOR A CACHE BLOCK WITH SPARSE DIRTY LINES 审中-公开
    用于具有稀疏线的高速缓存块的优化用户协调的系统和方法

    公开(公告)号：US20130326155A1

    公开(公告)日：2013-12-05

    申请号：US13483813

    申请日：2012-05-30

    申请人： Abhijeet Ashok Chachad

    发明人： Abhijeet Ashok Chachad

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0804 ,  G06F12/0822 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/621

    摘要： A system and method of optimized user coherence for a cache block with sparse dirty lines is disclosed wherein valid and dirty bits of each set are logically AND'ed together and the result for multiple sets are logically OR'ed together resulting in an indication whether a particular block has any dirty lines. If the result indicates that a block does not have dirty lines, then that entire block can be skipped from being written back without affecting coherency.

    摘要翻译： 公开了一种用于具有稀疏脏线的高速缓存块的用户相干优化的系统和方法，其中每组的有效位和脏位被逻辑地并入到一起，并且将多个集合的结果在逻辑上被或运算在一起，导致指示是否 特定块有任何脏线。 如果结果指示块没有脏线，则可以跳过整个块而不影响一致性。

    Asynchronous clock dividers to reduce on-chip variations of clock timing
    5.
    发明授权
    Asynchronous clock dividers to reduce on-chip variations of clock timing 有权
    异步时钟分频器可减少片上时钟时钟变化

    公开(公告)号：US08970267B2

    公开(公告)日：2015-03-03

    申请号：US12874627

    申请日：2010-09-02

    申请人： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    发明人： Raguram Damodaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    IPC分类号： H03K21/00 ,  H03K23/00 ,  H03K25/00 ,  H03K23/42

    CPC分类号： H03K25/00 ,  H03K23/42

    摘要： This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

    摘要翻译： 本发明是明确地确定在设计中使用的各种时钟沿的发生的一种手段，平衡集成电路内的各个位置处的时钟沿。 从外部源进入的时钟可能是片上变化（OCV）的来源，导致不可接受的时钟边缘偏移。 本发明将各种时钟分频器布置在使用这些时钟的远程位置的芯片上。 这最小化边缘发生的不确定性。

    Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing
    8.
    发明申请
    Asynchronous Clock Dividers to Reduce On-Chip Variations of Clock Timing 有权
    异步时钟分频器可降低时钟时序的片上变化

    公开(公告)号：US20130176060A1

    公开(公告)日：2013-07-11

    申请号：US12874627

    申请日：2010-09-02

    申请人： Raguram Modaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    发明人： Raguram Modaran ,  Abhijeet Ashok Chachad ,  Ramakrishnan Venkatasubramanian

    IPC分类号： H03K25/00

    CPC分类号： H03K25/00 ,  H03K23/42

    摘要： This invention is a means to definitively establish the occurrence of various clock edges used in a design, balancing clock edges at various locations within an integrated circuit. Clocks entering from outside sources can be a source of on-chip-variations (OCV) resulting in unacceptable clock edge skewing. The present invention arranges placement of the various clock dividers on the chip at remote locations where these clocks are used. This minimizes the uncertainty of the edge occurrence.

    摘要翻译： 本发明是明确地确定在设计中使用的各种时钟沿的发生的一种手段，平衡集成电路内的各个位置处的时钟沿。 从外部源进入的时钟可能是片上变化（OCV）的来源，导致不可接受的时钟边缘偏移。 本发明将各种时钟分频器布置在使用这些时钟的远程位置的芯片上。 这最小化边缘发生的不确定性。