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1.发明授权Efficient cache allocation by optimizing size and order of allocate commands based on bytes required by CPU 有权通过根据CPU所需的字节优化分配命令的大小和顺序，实现高效的缓存分配公开(公告)号：US08607000B2
公开(公告)日：2013-12-10
申请号：US13243411
申请日：2011-09-23
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
摘要翻译： 本发明是一种具有多级缓存系统的数据处理系统。 多级缓存系统至少包括第一级缓存和第二级高速缓存。 在所述至少一个第一级高速缓存和所述第二级高速缓存中的高速缓存未命中时，所述数据处理系统在所述第二级高速缓存内驱逐并分配高速缓存行。 数据处理系统从未命中地址确定请求是否落在所分配的高速缓存行的低一半或高一半内。 数据处理系统首先从缺失半高速缓存行的外部存储器请求数据。 当接收数据被提供给至少一个第一级高速缓存和CPU时。 数据处理系统然后从第二级高速缓存行的另一半请求来自外部存储器的数据。
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2.发明申请OPTIMIZING TAG FORWARDING IN A TWO LEVEL CACHE SYSTEM FROM LEVEL ONE TO LEVER TWO CONTROLLERS FOR CACHE COHERENCE PROTOCOL FOR DIRECT MEMORY ACCESS TRANSFERS 有权优化标签在两级高速缓存系统中从一级到两级控制器，用于直接存储器访问传输的高速缓存协议协议公开(公告)号：US20120191916A1
公开(公告)日：2012-07-26
申请号：US13245206
申请日：2011-09-26
申请人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
发明人： Abhijeet Ashok Chachad , Roger Kyle Castille , Joseph Raymond Michael Zbiciak , Dheera Balasubramanian
IPC分类号： G06F12/08
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A second level memory controller uses shadow tags 711 to implement snoop read and write coherence. These shadow tags are generally used only for snoops intending to keep L2 SRAM coherent with the level one data cache. Thus updates for all external cache lines are ignored. The shadow tags are updated on all level one cache allocates and all dirty and invalidate modifications to data stored in L2 SRAM. These interactions happen on different interfaces, but the traffic on that interface includes level one data cache accesses to both external and level two directly addressable lines. These interactions create extra traffic on these interfaces and creating extra stalls to the CPU. Thus in this invention shadow tags are updated only on a subset of less than all updates of the level one tags.
摘要翻译： 第二级内存控制器使用影子标签711来实现窥探读写一致性。 这些阴影标签通常仅用于snooping，以防止L2 SRAM与一级数据缓存保持一致。 因此，所有外部缓存行的更新都将被忽略。 阴影标签在所有级别的一个缓存分配上进行更新，并且对存储在L2 SRAM中的数据进行所有脏和无效修改。 这些交互发生在不同的接口上，但是该接口上的流量包括对外部和第二级直接可寻址线路的一级数据高速缓存访问。 这些交互在这些接口上创建额外的流量，并为CPU创建额外的停顿。 因此，在本发明中，仅在一级标签的所有更新的子集的子集上更新影子标签。
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公开(公告)号：US08560896B2
公开(公告)日：2013-10-15
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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公开(公告)号：US09195610B2
公开(公告)日：2015-11-24
申请号：US13241175
申请日：2011-09-22
IPC分类号： G06F12/12 , G06F7/483 , G06F9/30 , G06F11/10 , G06F13/16 , G06F13/18 , G06F1/32 , G06F12/02 , G06F13/364 , H03M13/35 , H03M13/29 , H03K19/00 , H03K21/00
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A shared resource within a module may be accessed by a request from an external requester. An external transaction request may be received from an external requester outside the module for access to the shared resource that includes control information, not all of which is needed to access the shared resource. The external transaction request may be modified to form a modified request by removing a portion of the locally unneeded control information and storing the unneeded portion of control information as an entry in a bypass buffer. A reply received from the shared resource may be modified by appending the stored portion of control information from the entry in the bypass buffer before sending the modified reply to the external requester.
摘要翻译： 模块内的共享资源可以通过来自外部请求者的请求来访问。 可以从模块外部的外部请求者接收外部事务请求，以访问包括控制信息的共享资源，而不是所有这些都需要访问共享资源。 外部事务请求可以被修改以通过去除局部不需要的控制信息的一部分并且将不需要的控制信息部分作为条目存储在旁路缓冲器中来形成修改的请求。 从共享资源接收到的答复可以通过在向外部请求者发送修改的回复之前，从旁路缓冲器中的条目附加控制信息的存储部分来修改。
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5.发明授权Requester based transaction status reporting in a system with multi-level memory 有权在具有多级内存的系统中基于请求者的事务状态报告公开(公告)号：US08732416B2
公开(公告)日：2014-05-20
申请号：US13239045
申请日：2011-09-21
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Ramakrishnan Venkatasubramanian , Dheera Balasubramanian , Naveen Bhoria
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A system has memory resources accessible by a central processing unit (CPU). One or more transaction requests are initiated by the CPU for access to one or more of the memory resources. Initiation of transaction requests is ceased for a period of time. The memory resources are monitored to determine when all of the transaction requests initiated by the CPU have been completed. An idle signal accessible by the CPU is provided that is asserted when all of the transaction requests initiated by the CPU have been completed.
摘要翻译： 系统具有可由中央处理单元（CPU）访问的存储器资源。 一个或多个事务请求由CPU启动以访问一个或多个存储器资源。 交易请求的启动停止一段时间。 监视内存资源，以确定CPU启动的所有事务请求何时完成。 提供由CPU访问的空闲信号，当由CPU发起的所有事务请求已经完成时，该信号被断言。
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公开(公告)号：US20120198272A1
公开(公告)日：2012-08-02
申请号：US13245164
申请日：2011-09-26
申请人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
发明人： Joseph Raymond Michael Zbiciak , Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian
IPC分类号： G06F11/16
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： This invention is an exception priority arbitration unit which prioritizes memory access permission fault and data exception signals according to a fixed hierarchy if received during a same cycle. A CPU memory access permission fault is prioritized above a DMA memory access permission fault of a direct memory access permission fault. Any memory access permission fault is prioritized above a data exception signal. A non-correctable data exception signal is prioritized above a correctable data exception signal.
摘要翻译： 本发明是一种异常优先仲裁单元，其在相同的周期内被接收时，根据固定层次来优先考虑存储器访问许可故障和数据异常信号。 CPU内存访问权限错误优先于直接内存访问许可故障的DMA内存访问权限错误。 任何存储器访问权限故障都优先于数据异常信号。 不可修正的数据异常信号优先于可纠正的数据异常信号。
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公开(公告)号：US20120079203A1
公开(公告)日：2012-03-29
申请号：US13241175
申请日：2011-09-22
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A shared resource within a module may be accessed by a request from an external requester. An external transaction request may be received from an external requester outside the module for access to the shared resource that includes control information, not all of which is needed to access the shared resource. The external transaction request may be modified to form a modified request by removing a portion of the locally unneeded control information and storing the unneeded portion of control information as an entry in a bypass buffer. A reply received from the shared resource may be modified by appending the stored portion of control information from the entry in the bypass buffer before sending the modified reply to the external requester.
摘要翻译： 模块内的共享资源可以通过来自外部请求者的请求来访问。 可以从模块外部的外部请求者接收外部事务请求，以访问包括控制信息的共享资源，而不是所有这些都需要访问共享资源。 外部事务请求可以被修改以通过去除局部不需要的控制信息的一部分并且将不需要的控制信息部分作为条目存储在旁路缓冲器中来形成修改的请求。 从共享资源接收到的答复可以通过在向外部请求者发送修改的回复之前，从旁路缓冲器中的条目附加控制信息的存储部分来修改。
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8.发明授权Managing bandwidth allocation in a processing node using distributed arbitration 有权使用分布式仲裁管理处理节点中的带宽分配公开(公告)号：US09075743B2
公开(公告)日：2015-07-07
申请号：US13237749
申请日：2011-09-20
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
IPC分类号： G06F13/16 , G06F11/10 , G06F7/483 , G06F9/30 , H03M13/35 , H03M13/29 , G06F13/18 , H03K19/00 , G06F1/32 , H03K21/00 , G06F12/02 , G06F13/364
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.
摘要翻译： 提供对包括多个请求者和多个目标资源的系统内对共享资源的访问的管理。 单独的仲裁点与每个目标资源相关联。 访问优先级值被分配给每个请求者。 执行仲裁比赛，以通过使用与第一目标资源相关联的第一仲裁点的两个或多个请求者的请求来访问第一目标资源来确定获胜请求者。 来自获胜请求者的请求被转发到第二目标资源。 执行第二仲裁比赛，以通过来自获胜请求者的转发请求访问第二目标资源，以及使用与第二目标资源相关联的第二仲裁点的来自一个或多个请求者的请求。
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9.发明授权Programmable mapping of external requestors to privilege classes for access protection 有权外部请求者可编程映射到访问保护的特权类公开(公告)号：US08683115B2
公开(公告)日：2014-03-25
申请号：US13239027
申请日：2011-09-21
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： A memory management and protection system that manages memory access requests from a number of requestors. Memory accesses are allowed or disallowed based on the privilege level of the requestor, based on a Privilege Identifier that accompanies each memory access request. An extended memory controller selects the appropriate set of segment registers based on the Privilege Identifier to insure that the request is compared to and translated by the segment register associated with the master originating the request. A set of mapping registers allow flexible mapping of each Privilege Identifier to the appropriate access permission.
摘要翻译： 一种管理来自多个请求者的存储器访问请求的存储器管理和保护系统。 基于每个存储器访问请求附带的权限标识符，基于请求者的权限级别允许或不允许内存访问。 扩展存储器控制器基于特权标识符选择适当的段寄存器集合，以确保请求被与发起请求的主机相关联的段寄存器进行比较和转换。 一组映射寄存器允许将每个权限标识符灵活映射到适当的访问权限。
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10.发明申请Managing Bandwidth Allocation in a Processing Node Using Distributed Arbitration 有权使用分布式仲裁管理处理节点中的带宽分配公开(公告)号：US20120290756A1
公开(公告)日：2012-11-15
申请号：US13237749
申请日：2011-09-20
申请人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
发明人： Raguram Damodaran , Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , David Quintin Bell
IPC分类号： G06F13/18
CPC分类号： G06F12/1081 , G06F1/3296 , G06F7/483 , G06F9/3012 , G06F11/1064 , G06F12/0246 , G06F12/0811 , G06F12/0815 , G06F12/12 , G06F13/1605 , G06F13/1652 , G06F13/1657 , G06F13/1663 , G06F13/18 , G06F13/364 , G06F2212/1021 , G06F2212/1032 , G06F2212/221 , G06F2212/2532 , G06F2212/283 , G06F2212/608 , H03K19/0016 , H03K21/00 , H03M13/2903 , H03M13/353 , Y02D10/124 , Y02D10/172 , Y02D50/20
摘要： Management of access to shared resources within a system comprising a plurality of requesters and a plurality of target resources is provided. A separate arbitration point is associated with each target resource. An access priority value is assigned to each requester. An arbitration contest is performed for access to a first target resource by requests from two or more of the requesters using a first arbitration point associated with the first target resource to determine a winning requester. The request from the winning requester is forwarded to a second target resource. A second arbitration contest is performed for access to the second target resource by the forwarded request from the winning requester and requests from one or more of the plurality of requesters using a second arbitration point associated with the second target resource.
摘要翻译： 提供对包括多个请求者和多个目标资源的系统内对共享资源的访问的管理。 单独的仲裁点与每个目标资源相关联。 访问优先级值被分配给每个请求者。 执行仲裁比赛，以通过使用与第一目标资源相关联的第一仲裁点的两个或多个请求者的请求来访问第一目标资源来确定获胜请求者。 来自获胜请求者的请求被转发到第二目标资源。 执行第二仲裁比赛，以通过来自获胜请求者的转发请求访问第二目标资源，以及使用与第二目标资源相关联的第二仲裁点的来自一个或多个请求者的请求。
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