发明授权
- 专利标题： Method and apparatus for powered off processor core mode
- 专利标题（中）： 关闭处理器核心模式的方法和设备
-
申请号： US12706631申请日： 2010-02-16
-
公开(公告)号： US08707062B2公开(公告)日： 2014-04-22
- 发明人: Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
- 申请人： Sanjeev Jahagirdar , Varghese George , John B. Conrad , Robert Milstrey , Stephen A. Fischer , Alon Naveh , Shai Rotem
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理商 Matthew C. Fagan
- 主分类号： G06F1/00
- IPC分类号： G06F1/00 ; G06F1/26 ; G06F12/00 ; G06F15/00 ; G06F11/00 ; G06F9/46
摘要：
For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.
公开/授权文献
信息查询
