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    Charge-saving power-gate apparatus and method
    2.
    发明授权
    Charge-saving power-gate apparatus and method 有权

    公开(公告)号：US09966940B2

    公开(公告)日：2018-05-08

    申请号：US13976156

    申请日：2011-09-23

    申请人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

    发明人： Shai Rotem ,  Norbert Unger ,  Michael Zelikson

    IPC分类号： H03K17/00 ,  H03K17/687 ,  G06F1/32 ,  G06F1/26 ,  H03K19/00

    CPC分类号： H03K17/00 ,  H03K17/687 ,  H03K2217/0036 ,  H03K2217/0063

    摘要： A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

    Parallel protection checking in an address translation look-aside buffer
    5.
    发明授权
    Parallel protection checking in an address translation look-aside buffer 失效
    地址转换后备缓冲区中的并行保护检查

    公开(公告)号：US5265227A

    公开(公告)日：1993-11-23

    申请号：US853008

    申请日：1992-03-17

    申请人： Leslie D. Kohn ,  Shai Rotem

    发明人： Leslie D. Kohn ,  Shai Rotem

    IPC分类号： G06F12/10 ,  G06F12/14

    CPC分类号： G06F12/1027

    摘要： A translation look-aside buffer is implemented utilizing a four-way set associative cache memory having four lines of 16 sets each. A virtual address tag and its corresponding physical address tag, as well as a number of status bits which control the type of access permitted for a given virtual address, are stored in the translation look-aside buffer. A portion of the inputted virtual address signal is used to provide a virtual address tag and is compared to the virtual address tag in the buffer memory. When the virtual address tag comparison is achieved, the physical address tags are provided as an output from the translation look-aside buffer. Also at the same time, a fault detection circuit performs various fault detection logic on the status bits, depending on the execution cycle being performed, such as read/write cycle or user/supervisor mode. If a hit occurs with one of the stored virtual address tags, its physical address tag is used, but only if a fault indication does not occur thereby generating a trap. The comparison of the virtual address tags, the generation of the physical address tag and checking of the status bits for fault detection is performed simultaneously in parallel so that only one clock cycle is needed to generate a physical address tag and a fault signal, if any, from the address translation look-aside buffer.

    摘要翻译： 使用具有四行每组16组的四路组关联高速缓冲存储器来实现翻译后备缓冲器。 虚拟地址标签及其对应的物理地址标签以及控制给定虚拟地址所允许的访问类型的多个状态位存储在翻译后备缓冲器中。 输入的虚拟地址信号的一部分用于提供虚拟地址标签，并将其与缓冲存储器中的虚拟地址标签进行比较。 当实现虚拟地址标签比较时，物理地址标签被提供为来自翻译后备缓冲器的输出。 同时，故障检测电路根据所执行的执行周期，例如读/写周期或用户/管理员模式，对状态位执行各种故障检测逻辑。 如果使用其中一个存储的虚拟地址标签发生命中，则使用其物理地址标记，但只有当不发生故障指示从而产生陷阱时。 虚拟地址标签的比较，物理地址标签的生成和故障检测的状态位的检查是并行执行的，因此只需要一个时钟周期来生成物理地址标签和故障信号（如果有的话） ，从地址转换后备缓冲区。

    Apparatus and method for parallel processing and self-timed serial marking of variable length instructions
    8.
    发明授权
    Apparatus and method for parallel processing and self-timed serial marking of variable length instructions 失效
    用于并行处理的装置和方法以及可变长度指令的自定时串行标记

    公开(公告)号：US5978899A

    公开(公告)日：1999-11-02

    申请号：US997457

    申请日：1997-12-23

    申请人： Ran Ginosar ,  Rakefet Kol ,  Kenneth Scott Stevens ,  Peter A. Beerel ,  Kenneth Yi Yun ,  Christopher John Myers ,  Shai Rotem

    发明人： Ran Ginosar ,  Rakefet Kol ,  Kenneth Scott Stevens ,  Peter A. Beerel ,  Kenneth Yi Yun ,  Christopher John Myers ,  Shai Rotem

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816

    摘要： Optimal parallelization of necessarily serial operations is performed by speculative parallel processing and propagation of serial marking signals to indicate valid data. An exemplary instruction marking circuit for a computer system implementing such optimization includes a series of columns, each column corresponding to one byte of a fixed length instruction line, and a length decoder in each column. Each length decoder receives a byte of the respective column, and performs a length decode independently of the other length decoders. The length decoder asserts a length signal indicative of an instruction length when the byte is the first byte of an instruction. A marking unit arrangement is coupled to the length decoders, and operates to mark each column containing a first byte of an instruction as a function of the length signals asserted by the length decoders.

    摘要翻译： 通过串行标记信号的推测性并行处理和传播来执行必要串行操作的最佳并行化，以指示有效数据。 实现这种优化的计算机系统的示例性指令标记电路包括一列列，每列对应于固定长度指令行的一个字节，以及每列中的长度解码器。 每个长度解码器接收相应列的字节，并且独立于其他长度解码器执行长度解码。 当字节是指令的第一个字节时，长度解码器确定指示指令长度的长度信号。 标记单元布置被耦合到长度解码器，并且操作以将包含指令的第一字节的每列标记为由长度解码器所确定的长度信号的函数。

    Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling
    9.
    发明授权
    Method and apparatus for controlling the saving of pipelines in pipelined processors during trap handling 失效
    在陷阱处理期间控制流水线处理器中管道节省的方法和装置

    公开(公告)号：US5574872A

    公开(公告)日：1996-11-12

    申请号：US265495

    申请日：1994-06-23

    申请人： Shai Rotem ,  Benny Lavi ,  Michael Kagan

    发明人： Shai Rotem ,  Benny Lavi ,  Michael Kagan

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3861 ,  G06F9/461

    摘要： A processor and method implemented in a processor, having a pipeline and trap generation capabilities, for indicating a pipelined instruction and for generating a trap upon modification of the pipeline. Improved trap handling capabilities and improved overall system performance is provided by reducing unnecessary saving and restoring of the pipeline during certain trap handling procedures, such as those that do not modify the state of the pipeline.

    摘要翻译： 一种在处理器中实现的处理器和方法，具有流水线和陷阱产生能力，用于指示流水线指令并且在修改管道时产生陷阱。 通过在某些陷阱处理过程中减少不必要的保存和恢复管道，例如不修改管道状态的陷阱处理过程，可以提供改进的陷阱处理能力和整体系统性能。