Invention Grant
US08796846B2 Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP
有权
具有三维FO-WLCSP垂直互连结构的半导体器件
- Patent Title: Semiconductor device with a vertical interconnect structure for 3-D FO-WLCSP
- Patent Title (中): 具有三维FO-WLCSP垂直互连结构的半导体器件
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Application No.: US12572590Application Date: 2009-10-02
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Publication No.: US08796846B2Publication Date: 2014-08-05
- Inventor: Yaojian Lin , Xusheng Bao , Kang Chen , Jianmin Fang
- Applicant: Yaojian Lin , Xusheng Bao , Kang Chen , Jianmin Fang
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Atkins & Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L27/00
- IPC: H01L27/00

Abstract:
A semiconductor device is made by forming a first conductive layer over a carrier. The first conductive layer has a first area electrically isolated from a second area of the first conductive layer. A conductive pillar is formed over the first area of the first conductive layer. A semiconductor die or component is mounted to the second area of the first conductive layer. A first encapsulant is deposited over the semiconductor die and around the conductive pillar. A first interconnect structure is formed over the first encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The carrier is removed. A portion of the first conductive layer is removed. The remaining portion of the first conductive layer includes an interconnect line and UBM pad. A second interconnect structure is formed over a remaining portion of the first conductive layer is removed.
Public/Granted literature
- US20100148360A1 Semiconductor Device and Method of Forming a Vertical Interconnect Structure for 3-D FO-WLCSP Public/Granted day:2010-06-17
Information query
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