Invention Grant
US08806405B2 Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design
有权
在集成电路设计中，产生网络拓扑模式作为路由信号路径的约束
- Patent Title: Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design
- Patent Title (中): 在集成电路设计中，产生网络拓扑模式作为路由信号路径的约束
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Application No.: US13665760Application Date: 2012-10-31
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Publication No.: US08806405B2Publication Date: 2014-08-12
- Inventor: Regis Colwell , Arnold Ginetti , Khalid ElGalaind , Thomas Jordan , Jose A. Martinez , Jeffrey Markham , Steven Riley , Chung-Do Yang
- Applicant: Cadence Design Systems, Inc.
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Kenyon & Kenyon LLP
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.
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