公开(公告)号：US10423750B1

公开(公告)日：2019-09-24

申请号：US15792618

申请日：2017-10-24

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Arnold Ginetti ,  Andrew Beckett

IPC: G06F17/50

Abstract: Disclosed herein are embodiments of systems, methods, and products providing technology database independent pcells to be seamlessly customized and implemented in a yet unknown IC package library. In particular, the technology database independent pcells may have a code to execute callback functions to retrieve the package library name of the parent cells hosting the pcells. Based upon the library name, the pcell code may access the technology files stored in the technology database of the package library of the parent cells to retrieve the layer name, layer number, the design resolution, and/or other information such as design rule information of the parent cells hosting the pcells. Based on the layer number, the resolution, and/or other information the pcells can configure for themselves correct layout geometry without any input from a circuit designer.

公开(公告)号：US10285276B1

公开(公告)日：2019-05-07

申请号：US15275230

申请日：2016-09-23

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Kukal ,  Arnold Ginetti ,  Steven R. Durrill ,  Abhay Agarwal ,  Vikas Kohli ,  Tyler Lockman

IPC: G06F11/22 ,  G06F17/50 ,  H05K3/00

Abstract: A method is provided that includes receiving shape data specifying a shape of an electromagnetic (EM) structure in a circuit layout and transferring the shape data to a schematic cell representation based on a logic function of the EM structure and package technology layers of the circuit layout. The method includes placing a symbol for the EM structure in the schematic cell representation, associating the shape data and a model path with a cell parameter in the symbol, mapping the shape data to the package technology layers, and specifying pins in the schematic cell representation according to the shape data. Further, the method includes verifying ports for the EM structure and placing the EM structure in a package layout for a printed circuit board (PCB). A system and a non-transitory, computer readable medium storing commands to perform the above method are also provided.

公开(公告)号：US10192020B1

公开(公告)日：2019-01-29

申请号：US15283081

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/00 ,  G06F17/50

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing dynamic maneuvers within virtual hierarchies of an electronic design. These techniques identify or generate a plurality of figure groups at one or more virtual hierarchies in a layout portion and receive a request to descend into or ascend from a figure group at a virtual hierarchy of the one or more virtual hierarchies. In response to the received request, these techniques update a layout view into an updated layout view at least by exposing layout design details in the figure group for native editing according to the request to descend into or ascend from the figure group and optionally synchronize a corresponding schematic design view according to the updated layout view.

公开(公告)号：US10055528B1

公开(公告)日：2018-08-21

申请号：US15282739

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5081 ,  G06F2217/74

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing engineering change orders (ECOs) with figure groups and virtual hierarchies. These techniques identify a schematic design and a layout having at least one virtual hierarchy of an electronic design. These techniques then implement an ECO to modify at least one layout circuit component design in a figure group, without considering a physical hierarchical structure of the layout. These techniques further check the figure group based in part or in whole upon one or more criteria and update one or more data structures for the at least one virtual hierarchy and the figure group based in part or in whole upon the ECO.

公开(公告)号：US09881120B1

公开(公告)日：2018-01-30

申请号：US14871735

申请日：2015-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Steven Durrill ,  Taranjit Singh Kukal

IPC: G06F17/50 ,  G06F7/76 ,  G06F1/26 ,  G06F15/78

CPC classification number: G06F17/5081 ,  G06F1/266 ,  G06F7/76 ,  G06F15/7867 ,  G06F17/5018 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5054 ,  G06F17/5063 ,  G06F2217/80 ,  H01L23/50 ,  H05K1/0203 ,  H05K3/0005

Abstract: Various embodiments implementing a multi-fabric mixed-signal electronic system design spanning across multiple design fabrics with electrical and/or thermal analysis awareness. A schematic design may be extracted from and a power delivery network (PDN) model may be determined from a plurality of layouts in multiple design fabrics in a multi-fabric design environment platform. A PDN-aware, multi-fabric full system schematic may be constructed by assembling the PDN model and the schematic design into the PDN-aware, multi-fabric full system schematic. For a schematic generated for a circuit block of interest, chip power models may be determined for the remaining portion of the multi-fabric mixed-signal electronic system design, and the PDN-aware, multi-fabric full system schematic may be updated by accounting for the chip power models. The circuit block of interest may then be electrically and/or thermally analyzed within the context of the remaining portion.

公开(公告)号：US09798840B1

公开(公告)日：2017-10-24

申请号：US14884730

申请日：2015-10-15

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti

IPC: G06F17/50 ,  G06F17/30

CPC classification number: G06F17/5009 ,  G06F17/5081

Abstract: Various embodiments are to a simulation platform with dynamic device model libraries and the implementation therefor. The simulation platform includes one or more servers hosting thereupon a database management system, a simulation frontend, and a simulation backend. The simulation frontend includes or is operatively coupled to one or more electronic design databases managed by a database management system, stored in a persistent storage device, and including design data in one or more domains across one or more design fabrics. The simulation backend includes or is operatively coupled to one or more simulators that perform simulations, analyzes, and/or optimizations for an electronic design by obtaining simulation inputs that are appended to the one or more electronic design databases or are stored in one or more separate data structures that are co-managed by the database management system.

公开(公告)号：US08527934B2

公开(公告)日：2013-09-03

申请号：US13692960

申请日：2012-12-03

Applicant: Cadence Design Systems, Inc.

Inventor： Arnold Ginetti ,  Theodore A. Paone ,  Gerard Tarroux ,  Jim Newton ,  Jean-Noel Pic

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068 ,  G06F17/5072

Abstract: Disclosed is an improved mechanism and method for implementing electronic designs. According to some approaches, a method, mechanism, and compute program product is disclosed for implementing electronic designs that allows visual editing of complex objects with advanced editing features, which also provides for automated correspondence of the editing results to parametric values for a programmable object in the design.

Abstract translation: 公开了一种用于实现电子设计的改进机制和方法。 根据一些方法，公开了一种用于实现电子设计的方法，机制和计算程序产品，其允许使用高级编辑特征对复杂对象进行可视编辑，其还提供编辑结果与可编程对象的参数值的自动对应 该设计。

公开(公告)号：US10133841B1

公开(公告)日：2018-11-20

申请号：US15282792

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Chayan Majumder ,  Arnold Ginetti ,  Chandra Prakash Manglani ,  Amit Kumar

IPC: G06F17/50

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

公开(公告)号：US09934354B1

公开(公告)日：2018-04-03

申请号：US15205593

申请日：2016-07-08

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Balvinder Singh ,  Steven R. Durrill ,  Arnold Ginetti ,  Vikrant Khanna ,  Abhishek Dabral ,  Madhur Sharma ,  Nikhil Gupta ,  Ritabrata Bhattacharya

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  G06F17/5077 ,  G06F2217/40 ,  G06F2217/74

Abstract: Disclosed are techniques for implementing a layout-driven, multi-fabric schematic design of an electronic design. These techniques identify a multi-fabric layout spanning across multiple design fabrics and layout connectivity information and determine a device map that correlates a first set of devices in the multi-fabric layout with respective parasitic models. The device map can be identified one or more pre-existing device maps or can be constructed anew. A multi-fabric schematic can be generated by using at least the respective parasitic models and the layout connectivity information.

公开(公告)号：US09881119B1

公开(公告)日：2018-01-30

申请号：US14754535

申请日：2015-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Taranjit Singh Kukal ,  Steven R. Durrill ,  Arnold Ginetti

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5036

Abstract: Disclosed are techniques for generating a parasitic-aware simulation schematic across multiple design fabrics. These techniques identify a first extracted model from existing extracted models for a first circuit component design in a first layout in a first design fabric of an electronic design that spans across multiple design fabrics. These techniques further generate a simulation schematic by inserting the first extracted model into the simulation schematic. In addition, a simulation may be performed with the simulation schematic to generate simulation results. Schematic models, if existing, may also be used to revise the simulation schematic. For circuit component designs corresponding to no extract models or schematic models, one or more extracted models placeable in the simulation schematic may also be constructed to update the simulation schematic.