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    EM-compliance topology in a tree router
    1.
    发明授权
    EM-compliance topology in a tree router 有权

    公开(公告)号：US10551431B1

    公开(公告)日：2020-02-04

    申请号：US15852875

    申请日：2017-12-22

    Applicant: Cadence Design Systems, Inc.

    Inventor： Chung-Do Yang ,  Hoi-Kuen Lam ,  John Mario Wilkosz

    IPC: G06F17/50 ,  G01R31/28

    Abstract: Described is an improved approach to implement EM analysis, where the analysis can be performed early stages of the design process. Tree-routing is implemented using a structural routing solution, where an automatic routing mechanism is performed to generate a complete routing tree. That routing tree is then used to perform topology-driven EM analysis at various stages of the design process.

    Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design
    4.
    发明授权
    Producing a net topology pattern as a constraint upon routing of signal paths in an integrated circuit design 有权
    在集成电路设计中，产生网络拓扑模式作为路由信号路径的约束

    公开(公告)号：US08806405B2

    公开(公告)日：2014-08-12

    申请号：US13665760

    申请日：2012-10-31

    Applicant: Cadence Design Systems, Inc.

    Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5077

    Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

    Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。

    PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN
    5.
    发明申请
    PRODUCING A NET TOPOLGY PATTERN AS A CONSTRAINT UPON ROUTING OF SIGNAL PATHS IN AN INTEGRATED CIRCUIT DESIGN 有权
    作为一个集成电路设计中的信号线路的布线的网格拓扑图

    公开(公告)号：US20140123094A1

    公开(公告)日：2014-05-01

    申请号：US13665760

    申请日：2012-10-31

    Applicant: CADENCE DESIGN SYSTEMS, INC.

    Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

    IPC: G06F17/50

    CPC classification number: G06F17/5077

    Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

    Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。

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