公开(公告)号：US09990461B1

公开(公告)日：2018-06-05

申请号：US15282632

申请日：2016-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Regis Colwell ,  Patrick Hyde ,  Akshat Shah ,  Jeremiah Cessna ,  Timothy Rosek ,  Khaled Elgalaind

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: A method for placing and routing devices in a circuit layout is provided. The method includes determining devices to be placed in a circuit layout and a relative position of two devices in the circuit layout. In some embodiments, the method includes pre-routing channels in the circuit layout, determining routing trunk information from the pre-routed channels, and placing the two devices in the circuit layout based on the routing trunk information. Further, the method includes forming a first routing trunk along channels in the circuit layout, coupling the first routing trunk to one device of the two devices, and checking that a placement of a plurality of devices and the coupling the first routing trunk to one device of the plurality of devices meet a circuit layout specification. A computer system and a non-transitory computer-readable medium storing commands to execute the above method are also provided.

公开(公告)号：US10699051B1

公开(公告)日：2020-06-30

申请号：US16024495

申请日：2018-06-29

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Regis Colwell ,  Hua Luo ,  Namita Rane ,  Elias L. Fallon

IPC: G06F30/392 ,  G06N5/04 ,  G06N20/00 ,  G06F111/04 ,  G06F111/20

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing layouts for an electronic design using machine learning, where users re-use patterns of layouts that have been previously implemented, and those previous patterns are applied to create recommendations in new situations. An improved approach to perform cross-validations is provided.

公开(公告)号：US09202000B1

公开(公告)日：2015-12-01

申请号：US14503271

申请日：2014-09-30

Applicant: Cadence Design Systems, Inc.

Inventor： Regis Colwell ,  Gilles Lamant ,  Jeremiah Emerson Cessna ,  Khaled M. Elgalaind ,  Haitham Gad ,  Hsun-Chieh Yu ,  Ming Yi Fang

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5068

Abstract: Systems and methods for creating and placing custom guard rings create a guard ring from a plurality of unit cells reflecting the devices that are enclosed in the guard ring. Using a unit cell identified by a design tool user as the basic unit of the guard ring, with a few additional setup parameters, a complete, content-aware guard ring is created. The guard ring will consist of a collection of the identified unit cells placed around the circuit devices that are to be protected. The created guard ring will function as a single circuit component. Edits to the dimensions and/or parameters of the unit cell will affect the placement of the unit cell in the protected area and will therefore require creation of a new guard ring consistent with the changed parameters.

Abstract translation: 用于创建和放置定制保护环的系统和方法从反映被封装在保护环中的装置的多个单元电池产生保护环。 使用由设计工具用户标识的单位单元作为保护环的基本单元，并使用一些其他设置参数，创建一个完整的内容感知保护环。 保护环将包括放置在要被保护的电路设备周围的识别的单元电池的集合。 创建的保护环将用作单个电路组件。 对单位单元的尺寸和/或参数的编辑将影响单位单元在保护区域中的位置，因此将需要创建与更改的参数一致的新保护环。

公开(公告)号：US08806405B2

公开(公告)日：2014-08-12

申请号：US13665760

申请日：2012-10-31

Applicant: Cadence Design Systems, Inc.

Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。

公开(公告)号：US20140123094A1

公开(公告)日：2014-05-01

申请号：US13665760

申请日：2012-10-31

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Regis Colwell ,  Arnold Ginetti ,  Khalid ElGalaind ,  Thomas Jordan ,  Jose A. Martinez ,  Jeffrey Markham ,  Steven Riley ,  Chung-Do Yang

IPC: G06F17/50

CPC classification number: G06F17/5077

Abstract: A method is provided to produce a constraint information for use to implement a routing process used to generate routing signal lines in an integrated circuit design comprising: producing a net topology pattern structure that corresponds to a logical net that is associated with at least two instance item structures of at least one functional design, wherein the net topology pattern structure is associated with the at least two instance item structures and includes multiple constituent structures that indicate at least one constraint upon physical implementation of the logical net structure.

Abstract translation: 提供了一种用于产生用于实现用于在集成电路设计中生成路由信号线的路由过程的约束信息的方法，包括：产生对应于与至少两个实例项目相关联的逻辑网络的网络拓扑模式结构 至少一个功能设计的结构，其中所述网络拓扑模式结构与所述至少两个实例项目结构相关联，并且包括指示所述逻辑网络结构的物理实现的至少一个约束的多个组成结构。