Invention Grant
- Patent Title: Method for manufacturing through-silicon via
- Patent Title (中): 硅通孔制造方法
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Application No.: US13176790Application Date: 2011-07-06
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Publication No.: US08828745B2Publication Date: 2014-09-09
- Inventor: Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
- Applicant: Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
- Applicant Address: TW Hsinchu
- Assignee: United Microelectronics Corp.
- Current Assignee: United Microelectronics Corp.
- Current Assignee Address: TW Hsinchu
- Agency: WPAT, PC
- Agent Justin King
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L21/306 ; H01L21/304 ; H01L21/768 ; H01L21/3105 ; H01L21/321

Abstract:
A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
Public/Granted literature
- US20130011938A1 METHOD FOR MANUFACTURING THROUGH-SILICON VIA Public/Granted day:2013-01-10
Information query
IPC分类: