发明授权
- 专利标题: Method for manufacturing through-silicon via
- 专利标题(中): 硅通孔制造方法
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申请号: US13176790申请日: 2011-07-06
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公开(公告)号: US08828745B2公开(公告)日: 2014-09-09
- 发明人: Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
- 申请人: Wei-Che Tsao , Chia-Lin Hsu , Jen-Chieh Lin , Teng-Chun Tsai , Hsin-Kuo Hsu , Ya-Hsueh Hsieh , Ren-Peng Huang , Chih-Hsien Chen , Wen-Chin Lin , Yung-Lun Hsieh
- 申请人地址: TW Hsinchu
- 专利权人: United Microelectronics Corp.
- 当前专利权人: United Microelectronics Corp.
- 当前专利权人地址: TW Hsinchu
- 代理机构: WPAT, PC
- 代理商 Justin King
- 主分类号: H01L21/66
- IPC分类号: H01L21/66 ; H01L21/306 ; H01L21/304 ; H01L21/768 ; H01L21/3105 ; H01L21/321
摘要:
A method for manufacturing TSVs, wherein the method comprises several steps as follows: A stack structure having a substrate and an ILD layer (inter layer dielectric layer) is provided, in which an opening penetrating through the ILD layer and further extending into the substrate is formed. After an insulator layer and a metal barrier layer are formed on the stack structure and the sidewalls of the opening, a top metal layer is then formed on the stack structure to fulfill the opening. A first planarization process stopping on the barrier layer is conducted to remove a portion of the top metal layer. A second planarization process stopping on the ILD layer is subsequently conducted to remove a portion of the metal barrier layer, a portion of the insulator layer and a portion of the top metal layer, wherein the second planarization process has a polishing endpoint determined by a light interferometry or a motor current.
公开/授权文献
- US20130011938A1 METHOD FOR MANUFACTURING THROUGH-SILICON VIA 公开/授权日:2013-01-10
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