发明授权
US08854897B2 Static random access memory apparatus and bit-line voltage controller thereof
有权
静态随机存取存储装置及其位线电压控制器
- 专利标题: Static random access memory apparatus and bit-line voltage controller thereof
- 专利标题(中): 静态随机存取存储装置及其位线电压控制器
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申请号: US13665941申请日: 2012-11-01
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公开(公告)号: US08854897B2公开(公告)日: 2014-10-07
- 发明人: Ching-Te Chuang , Nan-Chun Lien , Wei-Nan Liao , Chi-Hsin Chang , Hao-I Yang , Wei Hwang , Ming-Hsien Tu
- 申请人: Ching-Te Chuang , Nan-Chun Lien , Wei-Nan Liao , Chi-Hsin Chang , Hao-I Yang , Wei Hwang , Ming-Hsien Tu
- 申请人地址: TW Science-Based Industrial Park, Hsin-Chu TW Hsinchu
- 专利权人: Faraday Technology Corp.,National Chiao Tung University
- 当前专利权人: Faraday Technology Corp.,National Chiao Tung University
- 当前专利权人地址: TW Science-Based Industrial Park, Hsin-Chu TW Hsinchu
- 代理商 Winston Hsu; Scott Margo
- 优先权: TW101124623A 20120709
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.