公开(公告)号：US08854897B2

公开(公告)日：2014-10-07

申请号：US13665941

申请日：2012-11-01

申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC分类号： G11C7/10

CPC分类号： G11C11/413

摘要： A static random access memory apparatus and a bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

摘要翻译： 静态随机存取存储装置和位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

公开(公告)号：US20140009999A1

公开(公告)日：2014-01-09

申请号：US13665941

申请日：2012-11-01

申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

IPC分类号： G11C11/00

CPC分类号： G11C11/413

摘要： A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

摘要翻译： 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。