发明授权
US08866508B2 System and method for calibrating chips in a 3D chip stack architecture
有权
用于在3D芯片堆栈架构中校准芯片的系统和方法
- 专利标题： System and method for calibrating chips in a 3D chip stack architecture
- 专利标题（中）： 用于在3D芯片堆栈架构中校准芯片的系统和方法
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申请号： US13355024申请日： 2012-01-20
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公开(公告)号： US08866508B2公开(公告)日： 2014-10-21
- 发明人: Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
- 申请人： Ying-Yu Hsu , Ruey-Bin Sheen , Chih-Hsien Chang
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Duane Morris LLP
- 主分类号： G01R31/02
- IPC分类号： G01R31/02 ; G01R31/30 ; G01R31/26 ; G01R31/319 ; G01R31/3193
摘要：
A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.
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