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    SYSTEM AND METHOD FOR ALIGNING DATA BITS
    1.
    发明申请
    SYSTEM AND METHOD FOR ALIGNING DATA BITS 有权
    用于对准数据位的系统和方法

    公开(公告)号：US20140006883A1

    公开(公告)日：2014-01-02

    申请号：US13539519

    申请日：2012-07-02

    申请人： Ying-Yu HSU ,  Ruey-Bin SHEEN ,  Shih-Hung LAN ,  Chih-Hsien CHANG

    发明人： Ying-Yu HSU ,  Ruey-Bin SHEEN ,  Shih-Hung LAN ,  Chih-Hsien CHANG

    IPC分类号： G06F11/07

    CPC分类号： H04L25/14 ,  G06F13/1689

    摘要： Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

    摘要翻译： 公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。 实施例包括用于比较多组位的定时的分层结构。 其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

    Front-End Circuit of Low Supply-Voltage Memory Interface Receiver
    2.
    发明申请
    Front-End Circuit of Low Supply-Voltage Memory Interface Receiver 有权
    低电源电压存储器接口接收器的前端电路

    公开(公告)号：US20120249247A1

    公开(公告)日：2012-10-04

    申请号：US13077600

    申请日：2011-03-31

    申请人： Ying-Yu Hsu

    发明人： Ying-Yu Hsu

    IPC分类号： H03F3/04

    CPC分类号： H03F3/45179 ,  H03F2203/45506 ,  H03F2203/45646

    摘要： A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

    摘要翻译： 电路包括：参考电压发生器，被配置为产生第一参考电压和第二参考电压，其中所述第一参考电压高于正电源电压的一半，并且所述第二参考电压低于所述正电压的一半 电源电压。 n型差分放大器包括第一和第二NMOS晶体管，其中第一NMOS晶体管的栅极耦合到输入节点，并且第二NMOS晶体管的栅极被配置为接收第一参考电压。 p型差分放大器由正电源电压工作，并且包括第一和第二PMOS晶体管。 第一PMOS晶体管的栅极耦合到输入节点，并且第二PMOS晶体管的栅极被配置为接收第二参考电压。

    Impedance Calibration Circuit with Uniform Step Heights
    3.
    发明申请
    Impedance Calibration Circuit with Uniform Step Heights 有权
    具有均匀步距的阻抗校准电路

    公开(公告)号：US20110109422A1

    公开(公告)日：2011-05-12

    申请号：US12859920

    申请日：2010-08-20

    申请人： Ying-Yu Hsu

    发明人： Ying-Yu Hsu

    IPC分类号： H01C13/00

    CPC分类号： H01C13/00 ,  H01C10/50 ,  H03H7/40 ,  H03H11/30 ,  H03K17/163 ,  H04L25/0278

    摘要： An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

    摘要翻译： 集成电路包括第一连接线; 第二连接线; 多个调谐电阻器，每个具有序列号并且耦合在所述第一连接线和所述第二连接线之间; 以及多个开关，每个开关与多个调谐电阻器中的一个串联耦合。 多个调谐电阻器的序列号是连续的。 多个调谐电阻器的电阻值是各序列号的函数。

    Front-end circuit of low supply-voltage memory interface receiver
    5.
    发明授权
    Front-end circuit of low supply-voltage memory interface receiver 有权
    低电源电压存储器接口的前端电路

    公开(公告)号：US08324972B2

    公开(公告)日：2012-12-04

    申请号：US13077600

    申请日：2011-03-31

    申请人： Ying-Yu Hsu

    发明人： Ying-Yu Hsu

    IPC分类号： H03F3/04

    CPC分类号： H03F3/45179 ,  H03F2203/45506 ,  H03F2203/45646

    摘要： A circuit includes a reference voltage generator configured to generate a first reference voltage and a second reference voltage, wherein the first reference voltage is higher than a half of a positive power supply voltage, and the second reference voltage is lower than the half of the positive power supply voltage. An n-type differential amplifier includes a first and a second NMOS transistor, wherein a gate of the first NMOS transistor is coupled to an input node, and a gate of the second NMOS transistor is configured to receive the first reference voltage. A p-type differential amplifier is operated by the positive supply voltage and includes a first and a second PMOS transistor. A gate of the first PMOS transistor is coupled to the input node, and a gate of the second PMOS transistor is configured to receive the second reference voltage.

    摘要翻译： 电路包括：参考电压发生器，被配置为产生第一参考电压和第二参考电压，其中所述第一参考电压高于正电源电压的一半，并且所述第二参考电压低于所述正电压的一半 电源电压。 n型差分放大器包括第一和第二NMOS晶体管，其中第一NMOS晶体管的栅极耦合到输入节点，并且第二NMOS晶体管的栅极被配置为接收第一参考电压。 p型差分放大器由正电源电压工作，并且包括第一和第二PMOS晶体管。 第一PMOS晶体管的栅极耦合到输入节点，并且第二PMOS晶体管的栅极被配置为接收第二参考电压。

    Integrated circuits and methods for providing impedance of driver to drive data
    6.
    发明授权
    Integrated circuits and methods for providing impedance of driver to drive data 有权
    用于提供驱动器驱动数据阻抗的集成电路和方法

    公开(公告)号：US07940079B2

    公开(公告)日：2011-05-10

    申请号：US12723005

    申请日：2010-03-12

    申请人： Ying-Yu Hsu

    发明人： Ying-Yu Hsu

    IPC分类号： H03K17/16

    CPC分类号： H03K19/0005

    摘要： An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve. A portion of at least one of the first set of resistance data and the second set of resistance data is an impedance of the driver to drive data.

    摘要翻译： 集成电路包括与驱动器耦合的焊盘。 驾驶员能够将数据驱动到垫子上。 驱动器能够提供基本上适合于第一曲线的第一组电阻数据和基本上适合于第二曲线的第二组电阻数据。 第一组电阻数据和第二组电阻数据中的至少一个的一部分是驱动器驱动数据的阻抗。

    Impedance calibration circuit with uniform step heights
    7.
    发明授权
    Impedance calibration circuit with uniform step heights 有权
    具有均匀步长的阻抗校准电路

    公开(公告)号：US08362870B2

    公开(公告)日：2013-01-29

    申请号：US12859920

    申请日：2010-08-20

    申请人： Ying-Yu Hsu

    发明人： Ying-Yu Hsu

    IPC分类号： H01C13/00

    CPC分类号： H01C13/00 ,  H01C10/50 ,  H03H7/40 ,  H03H11/30 ,  H03K17/163 ,  H04L25/0278

    摘要： An integrated circuit includes a first connection line; a second connection line; a plurality of tuning resistors with each having a sequence number and being coupled between the first connection line and the second connection line; and a plurality of switches, with each being coupled in series with one of the plurality of tuning resistors. The sequence numbers of the plurality of tuning resistors are continuous. The resistance values of the plurality of tuning resistors are a function of the respective sequence numbers.

    摘要翻译： 集成电路包括第一连接线; 第二连接线; 多个调谐电阻器，每个具有序列号并且耦合在所述第一连接线和所述第二连接线之间; 以及多个开关，每个开关与多个调谐电阻器中的一个串联耦合。 多个调谐电阻器的序列号是连续的。 多个调谐电阻器的电阻值是各序列号的函数。

    High speed communication interface with an adaptive swing driver to reduce power consumption
    10.
    发明授权
    High speed communication interface with an adaptive swing driver to reduce power consumption 有权

    公开(公告)号：US08410818B1

    公开(公告)日：2013-04-02

    申请号：US13372978

    申请日：2012-02-14

    申请人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    发明人： Ying-Yu Hsu ,  Yung-Chow Peng ,  Min-Shueh Yuan ,  Chih-Hsien Chang

    IPC分类号： H03K19/094

    CPC分类号： H03K3/012 ,  H03K19/0013 ,  H03K19/018521

    摘要： A high-speed bus interface with an adaptive swing driver. A high speed interface includes a transmitter and a receiver coupled via a bus. The transmitter has an adaptive swing driver and a voltage-regulating-module (VRM). The adaptive swing driver includes a post-driver and a pre-driver. The post-driver provides an adaptive swing output with a dedicated adaptive voltage power supply (VDDQ) and transition emphasis driving capacity with an internal logic voltage supply (VDD). The pre-driver provides the transition emphasis driving capacity with a pull-up and a pull-down signal path to the post-driver. The voltage-regulating-module is configured to supply signal to the adaptive swing driver. The receiver includes a comparator and a bit-error-rate detector. The comparator amplifies the adaptive swing output received from the transmitter via a bus, while the bit-error-rate detector diagnoses the amplified adaptive swing output received from the comparator.