公开(公告)号：US20230334218A1

公开(公告)日：2023-10-19

申请号：US18313844

申请日：2023-05-08

Applicant: Ruey-Bin SHEEN ,  Tien-Chien HUANG ,  Chuan-Yao TAN

Inventor： Ruey-Bin SHEEN ,  Tien-Chien HUANG ,  Chuan-Yao TAN

IPC: G06F30/398 ,  G06F30/3953 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F30/3953

Abstract: The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

公开(公告)号：US08810268B2

公开(公告)日：2014-08-19

申请号：US12764346

申请日：2010-04-21

Applicant: Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

Inventor： Jui-Cheng Huang ,  Yung-Chow Peng ,  Ruey-Bin Sheen

IPC: G01R31/3187

CPC classification number: G09G3/3685 ,  G09G3/006 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

Abstract: A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

Abstract translation: 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。

公开(公告)号：US20140006883A1

公开(公告)日：2014-01-02

申请号：US13539519

申请日：2012-07-02

Applicant: Ying-Yu HSU ,  Ruey-Bin SHEEN ,  Shih-Hung LAN ,  Chih-Hsien CHANG

Inventor： Ying-Yu HSU ,  Ruey-Bin SHEEN ,  Shih-Hung LAN ,  Chih-Hsien CHANG

IPC: G06F11/07

CPC classification number: H04L25/14 ,  G06F13/1689

Abstract: Systems and methods are disclosed for aligning multiple data bits by adjusting the timing of input lines for those data bits. Embodiments include a hierarchical structure for comparing the timing of multiple sets of bits. Other embodiments include aligning data bits from multiple chips in a 3D die stacking architecture.

Abstract translation: 公开了通过调整这些数据位的输入线的定时来对准多个数据位的系统和方法。 实施例包括用于比较多组位的定时的分层结构。 其他实施例包括在3D管芯堆叠架构中对准来自多个芯片的数据位。

公开(公告)号：US20120235208A1

公开(公告)日：2012-09-20

申请号：US13048411

申请日：2011-03-15

Applicant: Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

Inventor： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

IPC: H01L29/12 ,  H01L21/66

CPC classification number: H01L27/0207

Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

Abstract translation: 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

公开(公告)号：US09287252B2

公开(公告)日：2016-03-15

申请号：US13048411

申请日：2011-03-15

Applicant: Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

Inventor： Chung-Hui Chen ,  Ruey-Bin Sheen ,  Yung-Chow Peng ,  Po-Zeng Kang ,  Chung-Peng Hsieh

IPC: H01L29/12 ,  H01L27/02

CPC classification number: H01L27/0207

Abstract: A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.

Abstract translation: 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。

公开(公告)号：US20080297200A1

公开(公告)日：2008-12-04

申请号：US11807521

申请日：2007-05-29

Applicant: Ruey-Bin Sheen

Inventor： Ruey-Bin Sheen

IPC: G01R25/00

CPC classification number: H03K5/1534 ,  H03K5/26

Abstract: A circuit for reducing phase distortion of a first signal and a second signal is provided, wherein the first and the second signals are complementary. The circuit includes a detecting circuit for detecting a first edge of the first signal and a second edge of the second signal, wherein the second edge immediately follows the first edge and is in a same direction as the first edge; an output node; and a signal regenerator connected to the detecting circuit and the output node. The signal regenerator is configured to generate an output signal having an additional first edge and an additional second edge. The additional first edge and the additional second edge are opposite edges substantially aligned to the first edge and the second edge, respectively. The additional first edge and the additional second edge are immediate neighboring edges.

Abstract translation: 提供了用于减少第一信号和第二信号的相位失真的电路，其中第一和第二信号是互补的。 该电路包括用于检测第一信号的第一边缘和第二信号的第二边缘的检测电路，其中第二边缘紧接着第一边缘并且处于与第一边缘相同的方向; 输出节点; 以及连接到检测电路和输出节点的信号再生器。 信号再生器被配置为产生具有附加的第一边缘和附加的第二边缘的输出信号。 附加的第一边缘和附加的第二边缘分别相对于第一边缘和第二边缘大致对准的相对边缘。 附加的第一边缘和附加的第二边缘是紧邻的边缘。

公开(公告)号：US07268712B1

公开(公告)日：2007-09-11

申请号：US11406947

申请日：2006-04-18

Applicant: Ruey-Bin Sheen

Inventor： Ruey-Bin Sheen

IPC: H03M1/10

CPC classification number: H04L25/0278

Abstract: An on-die calibration system includes an external reference component, a first and a second on-die adjustable components, and a calibration module coupled to the reference component, the first and second components, wherein the calibration module calibrates the first component according to the reference component and calibrates the second component according to the calibrated first component.

Abstract translation: 片上校准系统包括外部参考部件，第一和第二管芯上可调节部件以及耦合到参考部件第一和第二部件的校准模块，其中校准模块根据第一和第二部件校准第一部件 参考组件，并根据校准的第一组件校准第二组件。

公开(公告)号：US06310523B1

公开(公告)日：2001-10-30

申请号：US09566454

申请日：2000-05-08

Applicant: Oscal Tzyh-Chiang Chen ,  Robin Ruey-Bin Sheen

Inventor： Oscal Tzyh-Chiang Chen ,  Robin Ruey-Bin Sheen

IPC: H03B502

CPC classification number: H03K3/012 ,  H03K3/0315 ,  H03L7/0995

Abstract: A wide-range and low power consumption voltage-controlled oscillator according to the invention includes a logic control circuit, a parallel series controllable inverter bank and a voltage control load. The logic control circuit consists of a plurality of logic gates for receiving a selecting signal from an external device and then transmitting a control signal. The parallel series controllable inverter bank consists of a plurality of series controllable inverter banks electrically connected in parallel for receiving the control signal and outputting an oscillation signal, wherein the control signal is used to control the number of the series controllable inverter banks electrically connected in parallel. The voltage control load is electrically connected between the parallel series controllable inverter bank and ground for serving as a load of the parallel series controllable inverter bank.

Abstract translation: 根据本发明的宽范围和低功耗压控振荡器包括逻辑控制电路，并联串联可控逆变器组和电压控制负载。 逻辑控制电路由多个逻辑门组成，用于从外部设备接收选择信号，然后发送控制信号。 并联串联可控逆变器组由并联电连接的多个串联可控逆变器组组成，用于接收控制信号并输出​​振荡信号，其中控制信号用于控制并联电连接的串联可控逆变器组的数量 。 电压控制负载电连接在并联串联可控逆变器组和地之间，用作并联串联可控逆变器组的负载。

公开(公告)号：US08866508B2

公开(公告)日：2014-10-21

申请号：US13355024

申请日：2012-01-20

Applicant: Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

Inventor： Ying-Yu Hsu ,  Ruey-Bin Sheen ,  Chih-Hsien Chang

IPC: G01R31/02 ,  G01R31/30 ,  G01R31/26 ,  G01R31/319 ,  G01R31/3193

CPC classification number: H03K3/012 ,  G01R31/26 ,  G01R31/2607 ,  G01R31/3004 ,  G01R31/3191 ,  G01R31/31924 ,  G01R31/3193 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/0002 ,  H03K3/017 ,  H03K17/94 ,  H01L2924/00

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

Abstract translation: 公开了用于自适应地调整3D架构/堆叠中的第一和第二芯片之间的信号的驱动强度的系统和方法。 这可以用于在3D架构/堆栈中自适应地校准芯片。 该系统可以包括一个芯片上的传输电路和另一芯片上的接收器电路。 或者，系统可以仅在一个芯片上包括发送和接收电路。

公开(公告)号：US20110260746A1

公开(公告)日：2011-10-27

申请号：US12764346

申请日：2010-04-21

Applicant: Jui-Cheng HUANG ,  Yung-Chow PENG ,  Ruey-Bin SHEEN

Inventor： Jui-Cheng HUANG ,  Yung-Chow PENG ,  Ruey-Bin SHEEN

IPC: G01R31/02 ,  G01R31/26

CPC classification number: G09G3/3685 ,  G09G3/006 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2330/12

Abstract: A built-in self-test (BIST) circuit for a liquid crystal display (LCD) source driver includes at least one digital-to-analog converter (DAC) and at least one buffer coupled to the respective DAC, wherein the buffer is reconfigurable as a comparator. A first input signal and a second input signal are coupled to the comparator. The first input signal is a predetermined reference voltage level. The second input signal is a test offset voltage in a test range.

Abstract translation: 用于液晶显示器（LCD）源驱动器的内置自检（BIST）电路包括至少一个数模转换器（DAC）和耦合到相应DAC的至少一个缓冲器，其中缓冲器可重新配置 作为比较。 第一输入信号和第二输入信号耦合到比较器。 第一输入信号是预定的参考电压电平。 第二输入信号是测试范围内的测试偏移电压。