A signal processing circuit that consumes less power by stop of supply of power for a short time. In a storage element, before supply of power is stopped, data in a first storage circuit is stored to a second storage circuit, and the data is read from the second storage circuit and a verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. After supply of power is restarted, the data in the second storage circuit is stored to the first storage circuit, and the verification circuit can determine whether or not the data in the second storage circuit matches the data in the first storage circuit. In such a manner, verification can be performed without requiring a time for verification.