In-situ metal gate recess process for self-aligned contact application

Invention Grant

US08940597B2 In-situ metal gate recess process for self-aligned contact application 有权

Title translation: 用于自对准接触应用的原位金属浇口凹槽工艺

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Patent Title: In-situ metal gate recess process for self-aligned contact application
Patent Title (中): 用于自对准接触应用的原位金属浇口凹槽工艺
Application No.: US13792258

Application Date: 2013-03-11
Publication No.: US08940597B2

Publication Date: 2015-01-27
Inventor: Chia-Jung Hsu , Gin-Chen Huang , Yi-An Lin , Neng-Kuo Chen , Sey-Ping Sun , Clement Hsingjen Wann
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Applicant Address: TW Hsin-Chu
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
Current Assignee Address: TW Hsin-Chu
Agency: Duane Morris LLP
Main IPC: H01L21/8238
IPC: H01L21/8238 ; H01L29/40

In-situ metal gate recess process for self-aligned contact application

Abstract:

A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.

Abstract(Chinese):

一种制造金属栅极结构的方法。该方法包括在半导体衬底之上形成栅极结构，并执行一个或多个化学金属平面化（CMP）工艺，以使用CMP工具对形成的栅极结构进行平坦化。在CMP工具的CMP清洁器中执行原位栅极蚀刻工艺以形成栅极凹槽。然后可以将接触蚀刻停止层（CESL）沉积在所形成的栅极凹部中，并执行一个或多个CMP工艺以平坦化CESL。

Public/Granted literature

US20140256124A1 IN-SITU METAL GATE RECESS PROCESS FOR SELF-ALIGNED CONTACT APPLICATION Public/Granted day:2014-09-11

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Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS