公开(公告)号：US11450584B2

公开(公告)日：2022-09-20

申请号：US16997869

申请日：2020-08-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Ting Wang ,  Yi-An Lin ,  Ching-Chuan Chang ,  Po-Chang Kuo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L21/02 ,  H01L21/56

Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

公开(公告)号：US08940597B2

公开(公告)日：2015-01-27

申请号：US13792258

申请日：2013-03-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Jung Hsu ,  Gin-Chen Huang ,  Yi-An Lin ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/8238 ,  H01L29/40

CPC classification number: H01L29/401 ,  B24B37/042 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/67207 ,  H01L21/67219

Abstract: A method of producing a metal gate structure. The method includes forming a gate structure above a semiconductor substrate and performing one or more chemical metal planarization (CMP) processes to planarize the formed gate structure using a CMP tool. An in situ gate etching process is performed in a CMP cleaner of the CMP tool to form a gate recess. A contact etch stop layer (CESL) can then be deposited in the formed gate recess and one or more CMP processes performed to planarize the CESL.

Abstract translation: 一种制造金属栅极结构的方法。 该方法包括在半导体衬底之上形成栅极结构，并执行一个或多个化学金属平面化（CMP）工艺，以使用CMP工具对形成的栅极结构进行平坦化。 在CMP工具的CMP清洁器中执行原位栅极蚀刻工艺以形成栅极凹槽。 然后可以将接触蚀刻停止层（CESL）沉积在所形成的栅极凹部中，并执行一个或多个CMP工艺以平坦化CESL。

公开(公告)号：US20180138052A1

公开(公告)日：2018-05-17

申请号：US15855839

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Chia-Jung Hsu ,  Yi-An Lin

IPC: H01L21/321 ,  H01L21/683 ,  H01L21/673 ,  H01L21/02

CPC classification number: B24B37/30 ,  B24B37/04 ,  B24B37/10 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/0209 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/67046 ,  H01L21/67092 ,  H01L21/67219 ,  H01L21/673 ,  H01L21/683

Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.

公开(公告)号：US20170243733A1

公开(公告)日：2017-08-24

申请号：US15052310

申请日：2016-02-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Chia-Jung Hsu ,  Yi-An Lin

IPC: H01L21/02

CPC classification number: H01L21/32115 ,  B24B37/00 ,  H01L21/02013 ,  H01L21/02016 ,  H01L21/02054 ,  H01L21/0209 ,  H01L21/3212 ,  H01L21/673 ,  H01L21/683

Abstract: The present disclosure provides a semiconductor fabrication apparatus in accordance with one embodiment. The apparatus includes a wafer stage that is operable to secure and rotate a wafer; a polish head configured to polish a backside surface of the wafer; an air bearing module configured to apply an air pressure to a front surface of the wafer; and an edge sealing unit configured to seal edges of the wafer.

公开(公告)号：US12021002B2

公开(公告)日：2024-06-25

申请号：US17884286

申请日：2022-08-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Ting Wang ,  Yi-An Lin ,  Ching-Chuan Chang ,  Po-Chang Kuo

IPC: H01L23/31 ,  H01L21/02 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29

CPC classification number: H01L23/3171 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/563 ,  H01L23/291 ,  H01L23/3192 ,  H01L24/09 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A semiconductor die includes a semiconductor substrate, a dielectric layer over the semiconductor substrate, a metal structure in the dielectric layer, a first metal pad over the metal structure, a first oxide-based passivation layer over the first metal pad, a second oxide-based passivation layer over the first oxide-based passivation layer, and a bump electrically connected to the first metal pad. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

公开(公告)号：US11854898B2

公开(公告)日：2023-12-26

申请号：US17322007

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/78 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

CPC classification number: H01L21/823431 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823814 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/165 ,  H01L29/1608 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.

公开(公告)号：US10755995B2

公开(公告)日：2020-08-25

申请号：US16402042

申请日：2019-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yun-Ting Wang ,  Yi-An Lin ,  Ching-Chuan Chang ,  Po-Chang Kuo

IPC: H01L21/4763 ,  H01L23/31 ,  H01L23/00 ,  H01L23/29 ,  H01L21/02 ,  H01L21/56

Abstract: A method is provided. A bottom passivation layer is formed on a dielectric layer over a semiconductor substrate. Then, a first opening is formed in the bottom passivation layer to expose a portion of the dielectric layer. Next, a metal pad is formed in the first opening. Afterwards, a first oxide-based passivation layer is formed over the metal pad. Then, a second oxide-based passivation layer is formed over the first oxide-based passivation layer. The second oxide-based passivation layer has a hardness less than a hardness of the first oxide-based passivation layer.

公开(公告)号：US10391608B2

公开(公告)日：2019-08-27

申请号：US15855839

申请日：2017-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Hung Chen ,  Chia-Jung Hsu ,  Yi-An Lin

IPC: B24B37/30 ,  B24B37/10 ,  H01L21/67 ,  H01L21/02 ,  H01L21/321 ,  H01L21/673 ,  H01L21/683 ,  B24B37/04

Abstract: A wafer polishing apparatus is described herein. The wafer polishing apparatus includes a polish module configured to apply air pressure to a first surface of a wafer while performing a polishing process on a second surface of the wafer. In some implementations, the polish module is further configured to perform a cleaning process and/or a drying process on the second surface of the wafer, such that the same wafer polishing apparatus is configured to perform the polishing process, the cleaning process, and/or the drying process. In some implementations, the polishing module is further configured to air seal edges of the wafer during the polishing process, the cleaning process, and/or the drying process.

公开(公告)号：US09337103B2

公开(公告)日：2016-05-10

申请号：US13707769

申请日：2012-12-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-An Lin ,  Chun-Wei Chang ,  Neng-Kuo Chen ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/3205 ,  H01L21/8234

CPC classification number: H01L21/823437

Abstract: A method includes forming a first gate above a semiconductor substrate, forming a hard mask on the first gate, and forming a contact etch stop layer (CESL) on the hard mask. No hard mask is removed between the step of forming the hard mask and the step of forming the CESL. The method further includes forming an interlayer dielectric (ILD) layer over the CESL, and performing one or more CMP processes to planarize the ILD layer, remove the CESL on the hard mask, and remove at least one portion of the hard mask.

Abstract translation: 一种方法包括在半导体衬底上形成第一栅极，在第一栅极上形成硬掩模，以及在硬掩模上形成接触蚀刻停止层（CESL）。 在形成硬掩模的步骤和形成CESL的步骤之间没有去除硬掩模。 该方法还包括在CESL上形成层间电介质层（ILD）层，以及执行一个或多个CMP工艺以使ILD层平坦化，去除硬掩模上的CESL，以及去除硬掩模的至少一部分。

公开(公告)号：US20210272849A1

公开(公告)日：2021-09-02

申请号：US17322007

申请日：2021-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Li Wang ,  Neng-Kuo Chen ,  Ding-Kang Shih ,  Meng-Chun Chang ,  Yi-An Lin ,  Gin-Chen Huang ,  Chen-Feng Hsu ,  Hau-Yu Lin ,  Chih-Hsin Ko ,  Sey-Ping Sun ,  Clement Hsingjen Wann

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/161 ,  H01L29/16 ,  H01L29/06 ,  H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L29/51

Abstract: A fin structure is on a substrate. The fin structure includes an epitaxial region having an upper surface and an under-surface. A contact structure on the epitaxial region includes an upper contact portion and a lower contact portion. The upper contact portion includes a metal layer over the upper surface and a barrier layer over the metal layer. The lower contact portion includes a metal-insulator-semiconductor (MIS) contact along the under-surface. The MIS contact includes a dielectric layer on the under-surface and the barrier layer on the dielectric layer.