Invention Grant
- Patent Title: Method for stress reduced manufacturing semiconductor devices
- Patent Title (中): 降低制造半导体器件的应用方法
-
Application No.: US13679347Application Date: 2012-11-16
-
Publication No.: US08956960B2Publication Date: 2015-02-17
- Inventor: Peter Irsigler , Hans-Joachim Schulze
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/36 ; H01L21/762 ; C30B25/18 ; C30B25/04

Abstract:
According to an embodiment, a method for stress-reduced forming a semiconductor device includes: providing a semiconductor wafer including an upper side and a first semiconductor layer of a first semiconductor material at the upper side; forming, in a vertical cross-section which is substantially orthogonal to the upper side, at the upper side a plurality of first vertical trenches and a plurality of second vertical trenches between adjacent first vertical trenches so that the first vertical trenches have, in the vertical cross-section, a larger horizontal extension than the second vertical trenches; and forming a plurality of third semiconductor layers at the upper side which are, in the vertical cross-section, spaced apart from each other by gaps each of which overlaps, in the vertical cross-section, with a respective first vertical trench when seen from above. At least one of the third semiconductor layers includes a semiconductor material which is different to the first semiconductor material.
Public/Granted literature
- US20140141592A1 Method for Stress Reduced Manufacturing Semiconductor Devices Public/Granted day:2014-05-22
Information query
IPC分类: