Invention Grant
- Patent Title: Techniques for phase tuning for process optimization
- Patent Title (中): 用于过程优化的相位调整技术
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Application No.: US13997565Application Date: 2011-12-30
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Publication No.: US08959465B2Publication Date: 2015-02-17
- Inventor: Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
- Applicant: Paul A. Nyhus , Shem O. Ogadhoh , Swaminathan Sivakumar , Seongtae Jeong
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2011/068157 WO 20111230
- International Announcement: WO2013/101202 WO 20130704
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/36 ; G03F1/70

Abstract:
Techniques are provided for determining how thick or how deep to make the phased regions of a lithography mask. One example embodiment provides a method that includes: providing a first mask layout design including a first test set, and providing a second mask layout design including a second test set, wherein the second test set is larger than the first test set; simulating critical dimensions through focus of structures of interest in the first test set for a range of phase depths/thicknesses, and selecting an initial preferred mask phase depth/thickness based on results of the simulating; and generating a fast thick-mask model (FTM) at the initial preferred phase depth/thickness, and correcting the second test set of the second mask layout design using the FTM, thereby providing an optimized mask layout design. A mask having the optimized mask layout design may be implemented to give the optimum patterning.
Public/Granted literature
- US20140053117A1 TECHNIQUES FOR PHASE TUNING FOR PROCESS OPTIMIZATION Public/Granted day:2014-02-20
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