公开(公告)号：US09054215B2

公开(公告)日：2015-06-09

申请号：US13719113

申请日：2012-12-18

Applicant: Paul A. Nyhus ,  Swaminathan Sivakumar

Inventor： Paul A. Nyhus ,  Swaminathan Sivakumar

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/775 ,  H01L29/66 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L21/823487 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/02642 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

Abstract: Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical nanowire transistor, potentially based on one lithographic operation. In embodiments, DSA material is confined within a guide opening patterned using convention lithography. In embodiments, channel regions and gate electrode materials are aligned to edges of segregated regions within the DSA material.

Abstract translation: 定向自组装（DSA）材料或二嵌段共聚物可能基于一个光刻操作来最终限定垂直纳米线晶体管的栅电极的通道区域的特征。 在实施例中，DSA材料被限制在使用常规光刻图案化的引导开口内。 在实施例中，沟道区域和栅电极材料与DSA材料内的分离区域的边缘对准。

公开(公告)号：US20140017899A1

公开(公告)日：2014-01-16

申请号：US13976090

申请日：2011-12-29

Applicant: Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

Inventor： Charles H. Wallace ,  Swaminathan Sivakumar ,  Matthew L. Tingey ,  Chanaka D. Munasinghe ,  Nadia M. Rahhal-Orabi

IPC: H01L21/308

CPC classification number: H01L21/3088 ,  H01L21/0337

Abstract: Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be implemented with double patterning of a one- or two-dimensional photolithographic feature, for example. In some embodiments, the barrier layer is deposited to protect a first photoresist pattern prior to application of a second photoresist pattern thereon and/or to tailor (e.g., shrink) one or more of the critical dimensions of a trench, hole, or other etchable geometric feature to be formed in a substrate or other suitable surface via lithographic processes. In some embodiments, the techniques may be implemented to generate/print small features (e.g., less than or equal to about 100 nm) including one- and two-dimensional features/structures of varying complexity.

Abstract translation: 公开了使用图案层之间的阻挡层对光刻特征进行双重图案化的技术。 在一些情况下，例如，可以通过双图案化一维或二维光刻特征来实现这些技术。 在一些实施例中，沉积阻挡层以在施加第二光致抗蚀剂图案之前保护第一光致抗蚀剂图案和/或定制（例如，收缩）沟槽，孔或其它可蚀刻的一个或多个临界尺寸 通过光刻工艺在衬底或其它合适的表面中形成的几何特征。 在一些实施例中，可以实施技术来生成/打印包括不同复杂度的一维和二维特征/结构的小特征（例如，小于或等于约100nm）。

公开(公告)号：US08519462B2

公开(公告)日：2013-08-27

申请号：US13169864

申请日：2011-06-27

Applicant: Yih Wang ,  M. Clair Webb ,  Nick Lindert ,  Swaminathan Sivakumar ,  Kevin X. Zhang ,  Dinesh Somasekhar

Inventor： Yih Wang ,  M. Clair Webb ,  Nick Lindert ,  Swaminathan Sivakumar ,  Kevin X. Zhang ,  Dinesh Somasekhar

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/0207 ,  H01L27/10891

Abstract: A 6F2 DRAM cell with paired cells is described. In one embodiment the cell pairs are separated by n-type isolation transistors having gates defining dummy word lines. The dummy word lines are fabricated from a metal with a work function favoring p-channel devices.

Abstract translation: 描述了具有成对单元的6F2 DRAM单元。 在一个实施例中，单元对由具有限定虚拟字线的门的n型隔离晶体管分开。 虚拟字线由具有有利于p沟道器件的功函数的金属制成。

公开(公告)号：US07981756B2

公开(公告)日：2011-07-19

申请号：US12317656

申请日：2008-12-22

Applicant: Nick Lindert ,  Brian Doyle ,  Dinesh Somasekhar ,  Christopher J. Jezewski ,  Swaminathan Sivakumar ,  Kevin Zhang ,  Stephen Wu

Inventor： Nick Lindert ,  Brian Doyle ,  Dinesh Somasekhar ,  Christopher J. Jezewski ,  Swaminathan Sivakumar ,  Kevin Zhang ,  Stephen Wu

IPC: H01L21/20

CPC classification number: H01L27/101 ,  H01L28/90

Abstract: A process of forming a semiconductive capacitor device for a memory circuit includes forming a first capacitor cell recess and a second capacitor cell recess that are spaced apart by a capacitor cell boundary of a first height. The process includes lowering the first height of the capacitor cell boundary to a second height. A common plate capacitor bridges between the first recess and the second recess over the boundary above the second height and below the first height.

Abstract translation: 形成用于存储电路的半导体电容器器件的工艺包括形成由第一高度的电容器单元边界隔开的第一电容器单元凹槽和第二电容器单元凹槽。 该过程包括将电容器单元边界的第一高度降低到第二高度。 普通的平板电容器在第一凹槽和第二凹槽之间跨过第二高度并低于第一高度的边界。

公开(公告)号：US20090001431A1

公开(公告)日：2009-01-01

申请号：US11821971

申请日：2007-06-26

Applicant: Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

Inventor： Nadia Rahhal-Orabi ,  Charles H. Wallace ,  Alison Davis ,  Swaminathan Sivakumar

IPC: H01L29/78 ,  H01L21/4763

CPC classification number: H01L21/76804 ,  H01L21/76816 ,  H01L29/78

Abstract: In one embodiment of the invention, contact patterning may be divided into two or more passes which may allow designers to control the gate height critical dimension relatively independent from the contact top critical dimension.

Abstract translation: 在本发明的一个实施例中，接触图案化可以被分成两个或更多遍，这可以允许设计者相对独立于接触顶部临界尺寸来控制栅极高度临界尺寸。

公开(公告)号：US20070218685A1

公开(公告)日：2007-09-20

申请号：US11384143

申请日：2006-03-17

Applicant: Swaminathan Sivakumar ,  Charles Wallace ,  Alison Davis ,  Nadia Rahhal-Orabi

Inventor： Swaminathan Sivakumar ,  Charles Wallace ,  Alison Davis ,  Nadia Rahhal-Orabi

IPC: H01L21/44

CPC classification number: H01L21/76808 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/485

Abstract: A method to form transistor contacts begins with providing a transistor that includes a gate stack and first and second diffusion regions formed on a substrate, and a dielectric layer formed atop the gate stack and the diffusion regions. A first photolithography process forms first and second diffusion trench openings for the first and second diffusion regions. A sacrificial layer is then deposited into the first and second diffusion trench openings. Next, a second photolithography process forms a gate stack trench opening for the gate stack and a local interconnect trench opening coupling the gate stack trench opening to the first diffusion trench opening. The second photolithography process is carried out independent of the first photolithography process. The sacrificial layer is then removed and a metallization process is carried out to fill the first and second diffusion trench openings, the gate stack trench opening, and the local interconnect trench opening with a metal layer.

Abstract translation: 形成晶体管触点的方法开始于提供一种晶体管，该晶体管包括栅极堆叠以及形成在衬底上的第一和第二扩散区域，以及形成在栅极堆叠和扩散区域顶部的电介质层。 第一光刻工艺形成用于第一和第二扩散区域的第一和第二扩散沟槽开口。 然后将牺牲层沉积到第一和第二扩散沟槽开口中。 接下来，第二光刻工艺形成用于栅极堆叠的栅极堆叠沟槽开口和将栅极堆叠沟槽开口耦合到第一扩散沟槽开口的局部互连沟槽开口。 第二光刻工艺是独立于第一光刻工艺进行的。 然后去除牺牲层，并且进行金属化处理以填充第一和第二扩散沟槽开口，栅极堆叠沟槽开口和具有金属层的局部互连沟槽开口。

公开(公告)号：US07265431B2

公开(公告)日：2007-09-04

申请号：US10150197

申请日：2002-05-17

Applicant: Swaminathan Sivakumar

Inventor： Swaminathan Sivakumar

IPC: H01L31/0232 ,  H01L31/06

CPC classification number: G03F7/095 ,  G03F7/091 ,  H01L21/0276

Abstract: A semiconductor wafer may be coated with an imageable anti-reflective coating. As a result, the coating may be removed using the same techniques used to remove overlying photoresists. This may overcome the difficulty of etching anti-reflective coatings using standard etches because of their poor selectivity to photoresist and the resulting propensity to cause integrated circuit defects arising from anti-reflective coating remnants.

Abstract translation: 可以用可成像的抗反射涂层涂覆半导体晶片。 结果，可以使用用于去除覆盖的光致抗蚀剂的相同技术去除涂层。 这可以克服使用标准蚀刻来蚀刻抗反射涂层的难度，因为它们对光致抗蚀剂的选择性差，并导致由抗反射涂层残留物引起集成电路缺陷的倾向。

公开(公告)号：US20070128526A1

公开(公告)日：2007-06-07

申请号：US11297209

申请日：2005-12-07

Applicant: Charles Wallace ,  Shannon Daviess ,  Swaminathan Sivakumar

Inventor： Charles Wallace ,  Shannon Daviess ,  Swaminathan Sivakumar

IPC: G06F17/50 ,  G03F1/00

CPC classification number: G03F1/36

Abstract: Sub-resolution assist features for non-collinear features are described for use in photolithography. A photolithography mask with elongated features is synthesized. An end-to-end gap between two features if found for which the ends of the two features facing the gap are linearly offset from one another. A sub-resolution assist feature is applied to the end-to-end gap between the elongated features, and the synthesized photolithography mask is modified to include the sub-resolution assist feature.

Abstract translation: 描述了非共线特征的子分辨率辅助功能，用于光刻。 合成具有细长特征的光刻掩模。 如果发现两个特征面对间隙的两端的端部彼此线性偏移，则两个特征之间的端对端间隙。 子分辨率辅助特征被应用于细长特征之间的端到端间隙，并且合成的光刻掩模被修改为包括子分辨率辅助特征。

公开(公告)号：US20050148180A1

公开(公告)日：2005-07-07

申请号：US10750200

申请日：2003-12-30

Applicant: Swaminathan Sivakumar ,  Curtis Ward ,  Timothy Hehr ,  Mark Fradkin

Inventor： Swaminathan Sivakumar ,  Curtis Ward ,  Timothy Hehr ,  Mark Fradkin

IPC: H01L21/033 ,  H01L21/302 ,  H01L21/311 ,  H01L21/461 ,  H01L21/768 ,  H01L23/04 ,  H01L23/485

CPC classification number: H01L21/76804 ,  H01L21/0335 ,  H01L21/31144 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: The present invention relates to exposing a bond pad on a substrate. A bond pad is formed over a silicon substrate with the subsequent formation of a dielectric over the bond pad. A patterned resist is formed, and at least opening is processed to form a sloped sidewall profile. The sloped sidewall profile is subsequently etched and transferred to the dielectric layer, exposing the bond pad.

公开(公告)号：US20230207565A1

公开(公告)日：2023-06-29

申请号：US17561670

申请日：2021-12-23

Applicant: Abhishek Anil SHARMA ,  Wilfred GOMES ,  Swaminathan SIVAKUMAR ,  Mark C. PHILLIPS ,  Christopher M. PELTO

Inventor： Abhishek Anil SHARMA ,  Wilfred GOMES ,  Swaminathan SIVAKUMAR ,  Mark C. PHILLIPS ,  Christopher M. PELTO

IPC: H01L27/118 ,  H01L23/528

CPC classification number: H01L27/11807 ,  H01L23/5286 ,  H01L2027/11881

Abstract: Stitched dies having backside power delivery are described are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A signal line is coupling the first die and the second die at a first side of the first and second dies. A backside power rail is coupling the first die and the second die at a second side of the first and second dies, the second side opposite the first side.